ZHCSH89A
December 2017 – March 2018
MSP430FR5969-SP
PRODUCTION DATA.
1
器件概述
1.1
特性
1.2
应用
1.3
说明
1.4
功能框图
2
修订历史记录
3
Terminal Configuration and Functions
3.1
Pin Diagrams
3.2
Signal Descriptions
Signal Descriptions
3.3
Pin Multiplexing
3.4
Connection of Unused Pins
4
Specifications
4.1
Absolute Maximum Ratings
4.2
ESD Ratings
4.3
Recommended Operating Conditions
4.4
Active Mode Supply Current Into VCC Excluding External Current
4.5
Typical Characteristics – Active Mode Supply Currents
4.6
Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
4.7
Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
4.8
Low-Power Mode (LPM3.5, LPM4.5) Supply Currents (Into VCC) Excluding External Current
4.9
Typical Characteristics, Current Consumption per Module
4.10
Thermal Resistance Characteristics
4.11
Timing and Switching Characteristics
4.11.1
Power Supply Sequencing
Table 4-1
Brownout and Device Reset Power Ramp Requirements
Table 4-2
SVS
4.11.2
Reset Timing
Table 4-3
Reset Input
4.11.3
Clock Specifications
Table 4-4
Low-Frequency Crystal Oscillator, LFXT
Table 4-5
High-Frequency Crystal Oscillator, HFXT
Table 4-6
DCO
Table 4-7
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
Table 4-8
Module Oscillator (MODOSC)
4.11.4
Wake-up Characteristics
Table 4-9
Wake-up Times From Low-Power Modes and Reset
Table 4-10
Typical Wake-up Charge
4.11.4.1
Typical Characteristics, Average LPM Currents vs Wake-up Frequency
4.11.5
Digital I/Os
Table 4-11
Digital Inputs
Table 4-12
Digital Outputs
4.11.5.1
Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
Table 4-13
Pin-Oscillator Frequency, Ports Px
4.11.5.2
Typical Characteristics, Pin-Oscillator Frequency
4.11.6
Timer_A and Timer_B
Table 4-14
Timer_A
Table 4-15
Timer_B
4.11.7
eUSCI
Table 4-16
eUSCI (UART Mode) Clock Frequency
Table 4-17
eUSCI (UART Mode)
Table 4-18
eUSCI (SPI Master Mode) Clock Frequency
Table 4-19
eUSCI (SPI Master Mode)
Table 4-20
eUSCI (SPI Slave Mode)
Table 4-21
eUSCI (I2C Mode)
4.11.8
ADC
Table 4-22
12-Bit ADC, Power Supply and Input Range Conditions
Table 4-23
12-Bit ADC, Timing Parameters
Table 4-24
12-Bit ADC, Linearity Parameters With External Reference
Table 4-25
12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference
Table 4-26
12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference
Table 4-27
12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference
Table 4-28
12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference
Table 4-29
12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
Table 4-30
12-Bit ADC, Temperature Sensor and Built-In V1/2
Table 4-31
12-Bit ADC, External Reference
4.11.9
Reference
Table 4-32
REF, Built-In Reference
4.11.10
Comparator
Table 4-33
Comparator_E
4.11.11
FRAM
Table 4-34
FRAM
4.12
Emulation and Debug
Table 4-35
JTAG and Spy-Bi-Wire Interface
5
Detailed Description
5.1
Overview
5.2
CPU
5.3
Operating Modes
5.3.1
Peripherals in Low-Power Modes
5.3.1.1
Idle Currents of Peripherals in LPM3 and LPM4
5.4
Interrupt Vector Table and Signatures
5.5
Memory Organization
5.6
Bootloader (BSL)
5.7
JTAG Operation
5.7.1
JTAG Standard Interface
5.7.2
Spy-Bi-Wire Interface
5.8
FRAM
5.9
Memory Protection Unit Including IP Encapsulation
5.10
Peripherals
5.10.1
Digital I/O
5.10.2
Oscillator and Clock System (CS)
5.10.3
Power-Management Module (PMM)
5.10.4
Hardware Multiplier (MPY)
5.10.5
Real-Time Clock (RTC_B) (Only MSP430FR596x and MSP430FR594x)
5.10.6
Watchdog Timer (WDT_A)
5.10.7
System Module (SYS)
5.10.8
DMA Controller
5.10.9
Enhanced Universal Serial Communication Interface (eUSCI)
5.10.10
TA0, TA1
5.10.11
TA2, TA3
5.10.12
TB0
5.10.13
ADC12_B
5.10.14
Comparator_E
5.10.15
CRC16
5.10.16
AES256 Accelerator
5.10.17
True Random Seed
5.10.18
Shared Reference (REF)
5.10.19
Embedded Emulation
5.10.19.1
Embedded Emulation Module (EEM)
5.10.19.2
EnergyTrace++ Technology
5.10.20
Peripheral File Map
5.11
Input and Output Diagrams
5.11.1
Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
5.11.2
Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
5.11.3
Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
5.11.4
Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
5.11.5
Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
5.11.6
Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
5.11.7
Port P2 (P2.7) Input/Output With Schmitt Trigger
5.11.8
Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
5.11.9
Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger
5.11.10
Port P4 (P4.0 to P4.3) Input/Output With Schmitt Trigger
5.11.11
Port P4 (P4.4 to P4.7) Input/Output With Schmitt Trigger
5.11.12
Port PJ, PJ.4 and PJ.5 Input/Output With Schmitt Trigger
5.11.13
Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
5.11.14
Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
5.12
Device Descriptor (TLV)
5.13
Identification
5.13.1
Revision Identification
5.13.2
Device Identification
5.13.3
JTAG Identification
6
Applications, Implementation, and Layout
6.1
Software Best Practices for Radiation Effects Mitigation
6.2
Device Connection and Layout Fundamentals
6.2.1
Power Supply Decoupling and Bulk Capacitors
6.2.2
External Oscillator
6.2.3
JTAG
6.2.4
Reset
6.2.5
Unused Pins
6.2.6
General Layout Recommendations
6.2.7
Do's and Don'ts
6.3
Peripheral- and Interface-Specific Design Information
6.3.1
ADC12_B Peripheral
6.3.1.1
Partial Schematic
6.3.1.2
Design Requirements
6.3.1.3
Detailed Design Procedure
6.3.1.4
Layout Guidelines
7
器件和文档支持
7.1
入门和后续步骤
7.2
工具和软件
7.3
文档支持
7.4
辐射信息
7.5
相关链接
7.6
社区资源
7.7
商标
7.8
静电放电警告
7.9
出口管制提示
7.10
术语表
8
机械、封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
PHP|48
MPQF051B
RGZ|48
MPQF123F
散热焊盘机械数据 (封装 | 引脚)
PHP|48
PPTD117D
RGZ|48
QFND014T
订购信息
zhcsh89a_oa
zhcsh89a_pm
1.1
特性
抗辐射加固
扩展工作温度(-55°C 至 105°C)
(1)
单粒子闩锁 (SEL) 在 125°C 下的抗扰度可达 72 MeV.cm
2
/mg
辐射批次验收测试结果为 50krad
48 引脚 VQFN 塑料封装
单受控基线
延长了产品变更通知周期
产品可追溯性
延长了产品生命周期
1.
请参阅
规格
部分中的 MSP430FR5969-SP EM 寿命降额表。
嵌入式微控制器
时钟频率高达 16MHz 的 16 位精简指令集计算机 (RISC) 架构
宽电源电压范围
(1.8V 至 3.6V)
(2)
2.
最小电源电压受 SVS 电平限制。
优化的超低功率模式
工作模式:大约 100µA/MHz
待机(具有低功率低频内部时钟源 (VLO) 的 LPM3):0.4µA(典型值)
实时时钟 (LPM3.5):0.25µA(典型值)
(3)
关断 (LPM4.5):0.02µA(典型值)
3.
实时时钟 (RTC) 由 3.7pF 晶振计时。
超低功耗铁电 RAM (FRAM)
高达 64KB 的非易失性存储器
超低功耗写入
125ns 每个字的快速写入(4ms 内写入 64KB)
统一标准存储器 = 单个空间内的程序 + 数据 + 存储
10
15
写入周期持久性
抗辐射和非磁性
智能数字外设
32 位硬件乘法器 (MPY)
3 通道内部 DMA
具有日历和报警功能的实时时钟 (RTC)
5 个 16 位定时器,每个定时器具有多达 7 个捕捉/比较寄存器
16 位循环冗余校验器 (CRC)
高性能模拟
16 通道模拟比较器
12 位模数转换器 (ADC)
具有内部基准和采样保持
和高达 16 个外部输入通道
多功能输入/输出端口
可每位、每字节和每字访问(成对访问)
所有端口上,从 LPM 中的边沿可选唤醒
所有端口上可编程上拉和下拉
代码安全性和加密
128 位或 256 位 AES 安全加密和解密协处理器
(只适用于 MSP430FR59xx)
针对随机数生成算法的随机数种子
增强型串行通信
eUSCI_A0 和 eUSCI_A1 支持
支持自动波特率侦测的通用异步收发器 (UART)
IrDA 编码和解码
SPI
eUSCI_B0 支持
支持多个从器件寻址的 I
2
C
SPI
硬件 UART
灵活时钟系统
具有 10 个可选厂家调整频率的定频数控振荡器 (DCO)
低功率低频内部时钟源 (VLO)
32kHz 晶振 (LFXT)
高频晶振 (HFXT)
开发工具和软件
自由的专业开发环境 具有 EnergyTrace++™技术
开发套件 (
MSP-TS430RGZ48C
)
要获得完整的模块说明,请参见
《MSP430FR58xx,MSP430FR59xx,MSP430FR68xx 和 MSP430FR69xx 系列用户指南》