ZHCSH89A December   2017  – March 2018 MSP430FR5969-SP

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2修订历史记录
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagrams
    2. 3.2 Signal Descriptions
      1.      Signal Descriptions
    3. 3.3 Pin Multiplexing
    4. 3.4 Connection of Unused Pins
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 4.5  Typical Characteristics – Active Mode Supply Currents
    6. 4.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 4.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 4.8  Low-Power Mode (LPM3.5, LPM4.5) Supply Currents (Into VCC) Excluding External Current
    9. 4.9  Typical Characteristics, Current Consumption per Module
    10. 4.10 Thermal Resistance Characteristics
    11. 4.11 Timing and Switching Characteristics
      1. 4.11.1  Power Supply Sequencing
        1. Table 4-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 4-2 SVS
      2. 4.11.2  Reset Timing
        1. Table 4-3 Reset Input
      3. 4.11.3  Clock Specifications
        1. Table 4-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 4-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 4-6 DCO
        4. Table 4-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 4-8 Module Oscillator (MODOSC)
      4. 4.11.4  Wake-up Characteristics
        1. Table 4-9   Wake-up Times From Low-Power Modes and Reset
        2. Table 4-10 Typical Wake-up Charge
        3. 4.11.4.1    Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 4.11.5  Digital I/Os
        1. Table 4-11 Digital Inputs
        2. Table 4-12 Digital Outputs
        3. 4.11.5.1    Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
        4. Table 4-13 Pin-Oscillator Frequency, Ports Px
        5. 4.11.5.2    Typical Characteristics, Pin-Oscillator Frequency
      6. 4.11.6  Timer_A and Timer_B
        1. Table 4-14 Timer_A
        2. Table 4-15 Timer_B
      7. 4.11.7  eUSCI
        1. Table 4-16 eUSCI (UART Mode) Clock Frequency
        2. Table 4-17 eUSCI (UART Mode)
        3. Table 4-18 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 4-19 eUSCI (SPI Master Mode)
        5. Table 4-20 eUSCI (SPI Slave Mode)
        6. Table 4-21 eUSCI (I2C Mode)
      8. 4.11.8  ADC
        1. Table 4-22 12-Bit ADC, Power Supply and Input Range Conditions
        2. Table 4-23 12-Bit ADC, Timing Parameters
        3. Table 4-24 12-Bit ADC, Linearity Parameters With External Reference
        4. Table 4-25 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference
        5. Table 4-26 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference
        6. Table 4-27 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference
        7. Table 4-28 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference
        8. Table 4-29 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
        9. Table 4-30 12-Bit ADC, Temperature Sensor and Built-In V1/2
        10. Table 4-31 12-Bit ADC, External Reference
      9. 4.11.9  Reference
        1. Table 4-32 REF, Built-In Reference
      10. 4.11.10 Comparator
        1. Table 4-33 Comparator_E
      11. 4.11.11 FRAM
        1. Table 4-34 FRAM
    12. 4.12 Emulation and Debug
      1. Table 4-35 JTAG and Spy-Bi-Wire Interface
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  CPU
    3. 5.3  Operating Modes
      1. 5.3.1 Peripherals in Low-Power Modes
        1. 5.3.1.1 Idle Currents of Peripherals in LPM3 and LPM4
    4. 5.4  Interrupt Vector Table and Signatures
    5. 5.5  Memory Organization
    6. 5.6  Bootloader (BSL)
    7. 5.7  JTAG Operation
      1. 5.7.1 JTAG Standard Interface
      2. 5.7.2 Spy-Bi-Wire Interface
    8. 5.8  FRAM
    9. 5.9  Memory Protection Unit Including IP Encapsulation
    10. 5.10 Peripherals
      1. 5.10.1  Digital I/O
      2. 5.10.2  Oscillator and Clock System (CS)
      3. 5.10.3  Power-Management Module (PMM)
      4. 5.10.4  Hardware Multiplier (MPY)
      5. 5.10.5  Real-Time Clock (RTC_B) (Only MSP430FR596x and MSP430FR594x)
      6. 5.10.6  Watchdog Timer (WDT_A)
      7. 5.10.7  System Module (SYS)
      8. 5.10.8  DMA Controller
      9. 5.10.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 5.10.10 TA0, TA1
      11. 5.10.11 TA2, TA3
      12. 5.10.12 TB0
      13. 5.10.13 ADC12_B
      14. 5.10.14 Comparator_E
      15. 5.10.15 CRC16
      16. 5.10.16 AES256 Accelerator
      17. 5.10.17 True Random Seed
      18. 5.10.18 Shared Reference (REF)
      19. 5.10.19 Embedded Emulation
        1. 5.10.19.1 Embedded Emulation Module (EEM)
        2. 5.10.19.2 EnergyTrace++ Technology
      20. 5.10.20 Peripheral File Map
    11. 5.11 Input and Output Diagrams
      1. 5.11.1  Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
      2. 5.11.2  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
      3. 5.11.3  Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
      4. 5.11.4  Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
      5. 5.11.5  Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
      6. 5.11.6  Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
      7. 5.11.7  Port P2 (P2.7) Input/Output With Schmitt Trigger
      8. 5.11.8  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
      9. 5.11.9  Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger
      10. 5.11.10 Port P4 (P4.0 to P4.3) Input/Output With Schmitt Trigger
      11. 5.11.11 Port P4 (P4.4 to P4.7) Input/Output With Schmitt Trigger
      12. 5.11.12 Port PJ, PJ.4 and PJ.5 Input/Output With Schmitt Trigger
      13. 5.11.13 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
      14. 5.11.14 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    12. 5.12 Device Descriptor (TLV)
    13. 5.13 Identification
      1. 5.13.1 Revision Identification
      2. 5.13.2 Device Identification
      3. 5.13.3 JTAG Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Software Best Practices for Radiation Effects Mitigation
    2. 6.2 Device Connection and Layout Fundamentals
      1. 6.2.1 Power Supply Decoupling and Bulk Capacitors
      2. 6.2.2 External Oscillator
      3. 6.2.3 JTAG
      4. 6.2.4 Reset
      5. 6.2.5 Unused Pins
      6. 6.2.6 General Layout Recommendations
      7. 6.2.7 Do's and Don'ts
    3. 6.3 Peripheral- and Interface-Specific Design Information
      1. 6.3.1 ADC12_B Peripheral
        1. 6.3.1.1 Partial Schematic
        2. 6.3.1.2 Design Requirements
        3. 6.3.1.3 Detailed Design Procedure
        4. 6.3.1.4 Layout Guidelines
  7. 7器件和文档支持
    1. 7.1  入门和后续步骤
    2. 7.2  工具和软件
    3. 7.3  文档支持
    4. 7.4  辐射信息
    5. 7.5  相关链接
    6. 7.6  社区资源
    7. 7.7  商标
    8. 7.8  静电放电警告
    9. 7.9  出口管制提示
    10. 7.10 术语表
  8. 8机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3 文档支持

以下文档对 MSP430FR59xx MCU 进行了介绍。www.ti.com.cn 网站上提供了这些文档的副本。

接收文档更新通知

要接收文档更新通知（包括芯片勘误表），请转至 ti.com.cn 上您的器件对应的产品文件夹（关于产品文件夹的链接，请参见Section 7.5）。请单击右上角的“通知我”按钮。点击后，您将每周定期收到已更改的产品信息（如果有的话）。有关更改的详细信息，请查阅已修订文档的修订历史记录。

用户指南

    《通过 JTAG 接口对 MSP430 进行编程》本文档介绍了使用 JTAG 通信端口擦除、编程和验证基于 MSP430 闪存和 FRAM 的微控制器系列的存储器模块所需的功能。此外，该文档还描述了如何设定所有 MSP430 器件提供的 JTAG 访问安全熔丝。本文档介绍了使用标准 4 线 JTAG 接口和 2 线 JTAG 接口（也称为 Spy-Bi-Wire (SBW)）访问 MCU。
    《MSP430 硬件工具用户指南》本手册介绍了 TI MSP-FET430 闪存仿真工具 (FET) 的硬件。FET 是针对 MSP430 超低功耗微控制器的程序开发工具。对提供的接口类型，即并行端口接口和 USB 接口进行了说明。

应用报告

    MSP430 FRAM 技术 – 操作方法和最佳实践 FRAM 采用非易失性存储器技术，行为与 SRAM 类似，支持大量新 应用的同时，还改变了固件的设计方式。该应用程序报告从嵌入式软件开发方面概述了 FRAM 技术在 MSP430 中的使用方法和最佳实践。其中介绍了如何按照应用程序特定的代码、常量、数据空间要求实施存储器布局以及如何使用 FRAM 优化应用程序的能耗。
    MSP430 32kHz 晶体振荡器对于稳定的晶体振荡器，选择合适的晶振、正确的负载电路和适当的电路板布局布线至关重要。该应用报告总结了晶体振荡器的功能，介绍了为实现 MSP430 超低功耗运行而选择正确晶体的参数。此外，还给出了正确电路板布局布线的提示和示例。本文档还包含与可能振荡器测试相关的详细信息以确保大批量生产中的稳定振荡器运行。
    《MSP430 系统级 ESD 注意事项》系统级 ESD 对于低电压下的硅晶技术以及经济高效型和超低功耗组件的需求日益增加。该应用报告提出了三项不同的 ESD 主题，旨在帮助电路板设计人员和 OEM 理解并设计出稳健耐用的系统级设计。