ZHCSOU8B 数据表 | 德州仪器 TI.com.cn

ZHCSOU8B August 2021 – February 2022 MCT8316A

PRODUCTION DATA

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机械数据 (封装 | 引脚)

RGF|40
- MPQF173F

散热焊盘机械数据 (封装 | 引脚)

RGF|40
- QFND672

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8.7.4 Gate_Driver_Configuration Registers

#GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_TABLE_1 lists the memory-mapped registers for the Gate_Driver_Configuration registers. All register offset addresses not listed in #GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 8-50 GATE_DRIVER_CONFIGURATION Registers

Address	Acronym	Register Name	Section
ACh	GD_CONFIG1	Gate driver configuration 1	#GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GD_CONFIG1
AEh	GD_CONFIG2	Gate driver configuration 2	#GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GD_CONFIG2

Complex bit access types are encoded to fit into small table cells. #GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_LEGEND shows the codes that are used for access types in this section.

Table 8-51 Gate_Driver_Configuration Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

8.7.4.1 GD_CONFIG1 Register (Address = ACh) [Reset = 00228000h]

GD_CONFIG1 is shown in #GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GD_CONFIG1_FIGURE and described in #GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GD_CONFIG1_TABLE.

Return to the Summary Table.

Figure 8-72 GD_CONFIG1 Register

31	30	29	28	27	26	25	24
PARITY	RESERVED		RESERVED	SLEW_RATE		RESERVED
R/W-0h	R/W-0h		R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
RESERVED	RESERVED	RESERVED	RESERVED	OVP_SEL	OVP_EN	RESERVED	OTW_REP
R/W-0h	R/W-0h	R/W-1h	R/W-0h	R/W-0h	R/W-0h	R/W-1h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	RESERVED	OCP_DEG		OCP_RETRY	OCP_LVL	OCP_MODE
R/W-1h	R/W-0h	R/W-0h		R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
RESERVED	RESERVED	ADCOMP_TH_LS	ADCOMP_TH_HS	EN_ASR	EN_AAR	CSA_GAIN
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 8-52 GD_CONFIG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-29	RESERVED	R/W	0h	Reserved
28	RESERVED	R/W	0h	Reserved
27-26	SLEW_RATE	R/W	0h	Slew rate 0h = 25 V/µs 1h = 50 V/µs 2h = 125 V/µs 3h = 200 V/µs
25-24	RESERVED	R/W	0h	Reserved
23	RESERVED	R/W	0h	Reserved
22	RESERVED	R/W	0h	Reserved
21	RESERVED	R/W	1h	Reserved
20	RESERVED	R/W	0h	Reserved
19	OVP_SEL	R/W	0h	Overvoltage protection level 0h = VM overvoltage level is 32-V 1h = VM overvoltage level is 20-V
18	OVP_EN	R/W	0h	Overvoltage protection enable 0h = Disable 1h = Enable
17	RESERVED	R/W	1h	Reserved
16	OTW_REP	R/W	0h	Overtemperature warning reporting on nFAULT 0h = Over temperature reporting on nFAULT is disabled 1h = Over temperature reporting on nFAULT is enabled
15	RESERVED	R/W	1h	Reserved
14	RESERVED	R/W	0h	Reserved
13-12	OCP_DEG	R/W	0h	OCP deglitch time 0h = 0.2 µs 1h = 0.6 µs 2h = 1.1 µs 3h = 1.6 µs
11	OCP_RETRY	R/W	0h	OCP retry time 0h = 5 ms 1h = 500 ms
10	OCP_LVL	R/W	0h	OCP level 0h = 16 A (Typical) 1h = 24 A (Typical)
9-8	OCP_MODE	R/W	0h	OCP fault mode 0h = Overcurrent causes a latched fault 1h = Overcurrent causes an automatic retrying fault 2h = Overcurrent is report only but no action is taken 3h = Overcurrent is not reported and no action is taken
7	RESERVED	R/W	0h	Reserved
6	RESERVED	R/W	0h	Reserved
5	ADCOMP_TH_LS	R/W	0h	Active demag comparator threshold for low-side 0h = 100 mA 1h = 150 mA
4	ADCOMP_TH_HS	R/W	0h	Active demag comparator threshold for high-side 0h = 100 mA 1h = 150 mA
3	EN_ASR	R/W	0h	Active synchronous rectification enable 0h = Disable 1h = Enable
2	EN_AAR	R/W	0h	Active asynchronous rectification enable 0h = Disable 1h = Enable
1-0	CSA_GAIN	R/W	0h	Current Sense Amplifier (CSA) Gain 0h = 0.15 V/A 1h = 0.3 V/A 2h = 0.6 V/A 3h = 1.2 V/A

8.7.4.2 GD_CONFIG2 Register (Address = AEh) [Reset = 01200000h]

GD_CONFIG2 is shown in #GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GD_CONFIG2_FIGURE and described in #GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GD_CONFIG2_TABLE.

Return to the Summary Table.

Figure 8-73 GD_CONFIG2 Register

31	30	29	28	27	26	25	24
PARITY	DELAY_COMP_EN	TARGET_DELAY				BUCK_SR	BUCK_PS_DIS
R/W-0h	R/W-0h	R/W-0h				R/W-0h	R/W-1h

23	22	21	20	19	18	17	16
BUCK_CL	BUCK_SEL		BUCK_DIS	RESERVED
R/W-0h	R/W-1h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R/W-0h

7	6	5	4	3	2	1	0
RESERVED
R/W-0h

Table 8-53 GD_CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30	DELAY_COMP_EN	R/W	0h	Driver delay compensation enable 0h = Disable 1h = Enable
29-26	TARGET_DELAY	R/W	0h	Target delay 0h = Automatic based on slew rate 1h = 0.4 µs 2h = 0.6 µs 3h = 0.8 µs 4h = 1 µs 5h = 1.2 µs 6h = 1.4 µs 7h = 1.6 µs 8h = 1.8 µs 9h = 2 µs Ah = 2.2 µs Bh = 2.4 µs Ch = 2.6 µs Dh = 2.8 µs Eh = 3 µs Fh = 3.2 µs
25	BUCK_SR	R/W	0h	Buck slew rate 0h = Buck's FET slew rate is 1000V/µs 1h = Buck's FET slew rate is 200V/µs
24	BUCK_PS_DIS	R/W	1h	Buck power sequencing disable 0h = Buck power sequencing is enabled 1h = Buck power sequencing is disabled
23	BUCK_CL	R/W	0h	Buck current limit 0h = 600 mA 1h = 150 mA
22-21	BUCK_SEL	R/W	1h	Buck voltage selection 0h = Buck voltage is 3.3 V 1h = Buck voltage is 5.0 V 2h = Buck voltage is 4.0 V 3h = Buck voltage is 5.7 V
20	BUCK_DIS	R/W	0h	Buck disable 0h = Buck regulator is enabled 1h = Buck regulator is disabled
19-0	RESERVED	R/W	0h	Reserved