ZHCSCK8G May 2014 – October 2017 LP8860-Q1
PRODUCTION DATA.
Address 0x76
EEPROM Register 20 | |||||||
---|---|---|---|---|---|---|---|
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VDD_UVLO_
LEVEL |
RESERVED | CP_2X_CLK[1:0] | CP_2X_EN | SQW_PULSE_GEN_EN |
Name | Bit | Access | Description |
---|---|---|---|
VDD_UVLO_LEVEL | 7 | R/W | VDD UVLO protection level
0 = 2.5 V 1 = 3.0 V Voltage hysteresis typically 50 mV. 2.5V level can be used if PLL frequency up to 20 MHz. With higher PLL frequency logic is not specified to work down to 2.5 V VDD |
CP_2X_CLK[1:0] | 3:2 | R/W | Charge pump clock frequency
00 = 104 kHz 01 = 208 kHz 10 = 417 kHz 11 = 833 kHz |
CP_2X_EN | 1 | R/W | Charge pump enable. CP is enabled at soft start if CP_2X_EN EEPROM bit asserted.
0 = disabled 1 = enabled |
SQW_PULSE_GEN_EN | 0 | R/W | External charge pump clock enable (50% duty cycle 100 kHz). Clock connected to SQW pin. SQW clock enabled at soft start.
0 = disabled 1 = enabled |