ZHCSLT2C May   2020  – November 2022 LMK04832-SP

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 绝对最大额定值
    2. 6.2 ESD 等级
    3. 6.3 建议运行条件
    4. 6.4 热性能信息
    5. 6.5 电气特性
    6. 6.6 时序要求
    7. 6.7 Timing Diagram
    8. 6.8 典型特性
  7. 7 Parameter Measurement Information
    1. 7.1 Charge Pump Current Specification Definitions
      1. 7.1.1 Charge Pump Output Current Magnitude Variation vs Charge Pump Output Voltage
      2. 7.1.2 Charge Pump Sink Current vs Charge Pump Output Source Current Mismatch
      3. 7.1.3 Charge Pump Output Current Magnitude Variation vs Ambient Temperature
    2. 7.2 Differential Voltage Measurement Terminology
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Differences Between LMK04832-SP and LMK04832
        1. 8.1.1.1 Jitter Cleaning
        2. 8.1.1.2 JEDEC JESD204B Support
      2. 8.1.2 Clock Inputs
        1. 8.1.2.1 Inputs for PLL1
        2. 8.1.2.2 Inputs for PLL2
        3. 8.1.2.3 Inputs When Using Clock Distribution Mode
      3. 8.1.3 PLL1
        1. 8.1.3.1 Frequency Holdover
        2. 8.1.3.2 External VCXO for PLL1
      4. 8.1.4 PLL2
        1. 8.1.4.1 Internal VCOs for PLL2
        2. 8.1.4.2 External VCO Mode
      5. 8.1.5 Clock Distribution
        1. 8.1.5.1 Clock Divider
        2. 8.1.5.2 High Performance Divider Bypass Mode
        3. 8.1.5.3 SYSREF Clock Divider
        4. 8.1.5.4 Device Clock Delay
        5. 8.1.5.5 Dynamic Digital Delay
        6. 8.1.5.6 SYSREF Delay: Global and Local
        7. 8.1.5.7 Programmable Output Formats
        8. 8.1.5.8 Clock Output Synchronization
      6. 8.1.6 0-Delay
      7. 8.1.7 Status Pins
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Synchronizing PLL R Dividers
        1. 8.3.1.1 PLL1 R Divider Synchronization
        2. 8.3.1.2 PLL2 R Divider Synchronization
      2. 8.3.2 SYNC/SYSREF
      3. 8.3.3 JEDEC JESD204B
        1. 8.3.3.1 How to Enable SYSREF
          1. 8.3.3.1.1 Setup of SYSREF Example
          2. 8.3.3.1.2 SYSREF_CLR
        2. 8.3.3.2 SYSREF Modes
          1. 8.3.3.2.1 SYSREF Pulser
          2. 8.3.3.2.2 Continuous SYSREF
          3. 8.3.3.2.3 SYSREF Request
      4. 8.3.4 Digital Delay
        1. 8.3.4.1 Fixed Digital Delay
          1. 8.3.4.1.1 Fixed Digital Delay Example
        2. 8.3.4.2 Dynamic Digital Delay
        3. 8.3.4.3 Single and Multiple Dynamic Digital Delay Example
      5. 8.3.5 SYSREF to Device Clock Alignment
      6. 8.3.6 Input Clock Switching
        1. 8.3.6.1 Input Clock Switching - Manual Mode
        2. 8.3.6.2 Input Clock Switching - Pin Select Mode
        3. 8.3.6.3 Input Clock Switching - Automatic Mode
      7. 8.3.7 Digital Lock Detect
        1. 8.3.7.1 Calculating Digital Lock Detect Frequency Accuracy
      8. 8.3.8 Holdover
        1. 8.3.8.1 Enable Holdover
          1. 8.3.8.1.1 Fixed (Manual) CPout1 Holdover Mode
          2. 8.3.8.1.2 Tracked CPout1 Holdover Mode
        2. 8.3.8.2 During Holdover
        3. 8.3.8.3 Exiting Holdover
        4. 8.3.8.4 Holdover Frequency Accuracy and DAC Performance
      9. 8.3.9 PLL2 Loop Filter
    4. 8.4 Device Functional Modes
      1. 8.4.1 DUAL PLL
        1. 8.4.1.1 Dual Loop
        2. 8.4.1.2 Dual Loop With Cascaded 0-Delay
        3. 8.4.1.3 Dual Loop With Nested 0-Delay
      2. 8.4.2 Single PLL
        1. 8.4.2.1 PLL2 Single Loop
        2. 8.4.2.2 PLL2 With External VCO
      3. 8.4.3 Distribution Mode
    5. 8.5 Programming
      1. 8.5.1 Recommended Programming Sequence
    6. 8.6 Register Maps
      1. 8.6.1 Register Map for Device Programming
      2. 8.6.2 Device Register Descriptions
        1. 8.6.2.1 System Functions
          1. 8.6.2.1.1 RESET, SPI_3WIRE_DIS
          2. 8.6.2.1.2 POWERDOWN
          3. 8.6.2.1.3 ID_DEVICE_TYPE
          4. 8.6.2.1.4 ID_PROD
          5. 8.6.2.1.5 ID_MASKREV
          6. 8.6.2.1.6 ID_VNDR
        2. 8.6.2.2 (0x100 - 0x138) Device Clock and SYSREF Clock Output Controls
          1. 8.6.2.2.1 DCLKX_Y_DIV
          2. 8.6.2.2.2 DCLKX_Y_DDLY
          3. 8.6.2.2.3 CLKoutX_Y_PD, CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKX_Y_DDLY_PD, DCLKX_Y_DDLY[9:8], DCLKX_Y_DIV[9:8]
          4. 8.6.2.2.4 CLKoutX_SRC_MUX, CLKoutX_Y_PD, DCLKX_Y_BYP, DCLKX_Y_DCC, DCLKX_Y_POL, DCLKX_Y_HS
          5. 8.6.2.2.5 CLKoutY_SRC_MUX, SCLKX_Y_PD, SCLKX_Y_DIS_MODE, SCLKX_Y_POL, SCLKX_Y_HS
          6. 8.6.2.2.6 SCLKX_Y_ADLY_EN, SCLKX_Y_ADLY
          7. 8.6.2.2.7 SCLKX_Y_DDLY
          8. 8.6.2.2.8 CLKoutY_FMT, CLKoutX_FMT
        3. 8.6.2.3 SYSREF, SYNC, and Device Config
          1. 8.6.2.3.1  VCO_MUX, OSCout_MUX, OSCout_FMT
          2. 8.6.2.3.2  SYSREF_REQ_EN, SYNC_BYPASS, SYSREF_MUX
          3. 8.6.2.3.3  SYSREF_DIV
          4. 8.6.2.3.4  SYSREF_DDLY
          5. 8.6.2.3.5  SYSREF_PULSE_CNT
          6. 8.6.2.3.6  PLL2_RCLK_MUX, PLL2_NCLK_MUX, PLL1_NCLK_MUX, FB_MUX, FB_MUX_EN
          7. 8.6.2.3.7  PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD, SYSREF_PLSR_PD
          8. 8.6.2.3.8  DDLYdSYSREF_EN, DDLYdX_EN
          9. 8.6.2.3.9  DDLYd_STEP_CNT
          10. 8.6.2.3.10 SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD, SYNC_MODE
          11. 8.6.2.3.11 SYNC_DISSYSREF, SYNC_DISX
          12. 8.6.2.3.12 PLL1R_SYNC_EN, PLL1R_SYNC_SRC, PLL2R_SYNC_EN, FIN0_DIV2_EN, FIN0_INPUT_TYPE
        4. 8.6.2.4 (0x146 - 0x149) CLKin Control
          1. 8.6.2.4.1 CLKin_SEL_PIN_EN, CLKin_SEL_PIN_POL, CLKin2_EN, CLKin1_EN, CLKin0_EN, CLKin2_TYPE, CLKin1_TYPE, CLKin0_TYPE
          2. 8.6.2.4.2 CLKin_SEL_AUTO_REVERT_EN, CLKin_SEL_AUTO_EN, CLKin_SEL_MANUAL, CLKin1_DEMUX, CLKin0_DEMUX
          3. 8.6.2.4.3 CLKin_SEL0_MUX, CLKin_SEL0_TYPE
          4. 8.6.2.4.4 SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE
        5. 8.6.2.5 RESET_MUX, RESET_TYPE
        6. 8.6.2.6 (0x14B - 0x152) Holdover
          1. 8.6.2.6.1 LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8]
          2. 8.6.2.6.2 MAN_DAC
          3. 8.6.2.6.3 DAC_TRIP_LOW
          4. 8.6.2.6.4 DAC_CLK_MULT, DAC_TRIP_HIGH
          5. 8.6.2.6.5 DAC_CLK_CNTR
          6. 8.6.2.6.6 CLKin_OVERRIDE, HOLDOVER_EXIT_MODE, HOLDOVER_PLL1_DET, LOS_EXTERNAL_INPUT, HOLDOVER_VTUNE_DET, CLKin_SWITCH_CP_TRI, HOLDOVER_EN
          7. 8.6.2.6.7 HOLDOVER_DLD_CNT
        7. 8.6.2.7 (0x153 - 0x15F) PLL1 Configuration
          1. 8.6.2.7.1 CLKin0_R
          2. 8.6.2.7.2 CLKin1_R
          3. 8.6.2.7.3 CLKin2_R
          4. 8.6.2.7.4 PLL1_N
          5. 8.6.2.7.5 PLL1_WND_SIZE, PLL1_CP_TRI, PLL1_CP_POL, PLL1_CP_GAIN
          6. 8.6.2.7.6 PLL1_DLD_CNT
          7. 8.6.2.7.7 HOLDOVER_EXIT_NADJ
          8. 8.6.2.7.8 PLL1_LD_MUX, PLL1_LD_TYPE
        8. 8.6.2.8 (0x160 - 0x16E) PLL2 Configuration
          1. 8.6.2.8.1 PLL2_R
          2. 8.6.2.8.2 PLL2_P, OSCin_FREQ, PLL2_REF_2X_EN
          3. 8.6.2.8.3 PLL2_N_CAL
          4. 8.6.2.8.4 PLL2_N
          5. 8.6.2.8.5 PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI
          6. 8.6.2.8.6 PLL2_DLD_CNT
          7. 8.6.2.8.7 PLL2_LD_MUX, PLL2_LD_TYPE
        9. 8.6.2.9 (0x16F - 0x555) Misc Registers
          1. 8.6.2.9.1 PLL2_PRE_PD, PLL2_PD, FIN0_PD
          2. 8.6.2.9.2 PLL1R_RST
          3. 8.6.2.9.3 CLR_PLL1_LD_LOST, CLR_PLL2_LD_LOST
          4. 8.6.2.9.4 RB_PLL1_LD_LOST, RB_PLL1_LD, RB_PLL2_LD_LOST, RB_PLL2_LD
          5. 8.6.2.9.5 RB_DAC_VALUE (MSB), RB_CLKinX_SEL, RB_CLKinX_LOS
          6. 8.6.2.9.6 RB_DAC_VALUE
          7. 8.6.2.9.7 RB_HOLDOVER
          8. 8.6.2.9.8 SPI_LOCK
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Treatment of Unused Pins
      2. 9.1.2 Digital Lock Detect Frequency Accuracy
        1. 9.1.2.1 Minimum Lock Time Calculation Example
      3. 9.1.3 Driving CLKin AND OSCin Inputs
        1. 9.1.3.1 Driving CLKin and OSCin PINS With a Differential Source
        2. 9.1.3.2 Driving CLKin Pins With a Single-Ended Source
      4. 9.1.4 OSCin Doubler for Best Phase Noise Performance
      5. 9.1.5 Radiation Environments
        1. 9.1.5.1 Total Ionizing Dose
        2. 9.1.5.2 Single Event Effect
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Device Selection
          1. 9.2.2.1.1 Clock Architect
        2. 9.2.2.2 Device Configuration and Simulation
        3. 9.2.2.3 Device Programming
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Cold Sparing Considerations
        1. 9.3.1.1 Damage Prevention Details to Unpowered Device
      2. 9.3.2 Current Consumption
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Thermal Management
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Clock Architect
        2. 10.1.1.2 PLLatinum Sim
        3. 10.1.1.3 TICS Pro
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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订购信息

8.6.1 Register Map for Device Programming

Table 8-6 provides the register map for device programming. Any register can be read from the same data address it is written to.

Table 8-6 Register Map
ADDRESS
[14:0]		DATA[7:0]
23:876543210
0x000RESET00SPI_3WIRE
_DIS		0000
0x0020000000POWER
DOWN
0x003ID_DEVICE_TYPE
0x004ID_PROD[15:8]
0x005ID_PROD[7:0]
0x006ID_MASKREV
0x00CID_VNDR[15:8]
0x00DID_VNDR[7:0]
0x100DCLK0_1_DIV[7:0]
0x101DCLK0_1_DDLY[7:0]
0x102CLKout0_1_PDCLKout0_1_ODLCLKout0_1_IDLDCLK0_1_DDLY_PDDCLK0_1_DDLY[9:8]DCLK0_1_DIV[9:8]
0x10301CLKout0_SRC_MUXDCLK0_1_PDDCLK0_1_BYPDCLK0_1_DCCDCLK0_1_POLDCLK0_1_HS
0x10400CLKout1_SRC_MUXSCLK0_1_PDSCLK0_1_DIS_MODESCLK0_1_POLSCLK0_1_HS
0x10500SCLK0_1_ADLY_ENSCLK0_1_ADLY
0x1060000SCLK0_1_DDLY
0x107CLKout1_FMTCLKout0_FMT
0x108DCLK2_3_DIV[7:0]
0x109DCLK2_3_DDLY[7:0]
0x10ACLKout2_3_PDCLKout2_3_ODLCLKout2_3_IDLDCLK2_3_DDLY_PDDCLK2_3_DDLY[9:8]DCLK2_3_DIV[9:8]
0x10B01CLKout2_SRC_MUXDCLK2_3_PDDCLK2_3_BYPDCLK2_3_DCCDCLK2_3_POLDCLK2_3_HS
0x10C00CLKout3_SRC_MUXSCLK2_3_PDSCLK2_3_DIS_MODESCLK2_3_POLSCLK2_3_HS
0x10D00SCLK2_3_ADLY_ENSCLK2_3_ADLY
0x10E0000SCLK2_3_DDLY
0x10FCLKout3_FMTCLKout2_FMT
0x110DCLK4_5_DIV[7:0]
0x111DCLK4_5_DDLY[7:0]
0x112CLKout4_5_PDCLKout4_5_ODLCLKout4_5_IDLDCLK4_5_DDLY_PDDCLK4_5_DDLY[9:8]DCLK4_5_DIV[9:8]
0x11301CLKout4_SRC_MUXDCLK4_5_PDDCLK4_5_BYPDCLK4_5_DCCDCLK4_5_POLDCLK4_5_HS
0x11400CLKout5_SRC_MUXSCLK4_5_PDSCLK4_5_DIS_MODESCLK4_5_POLSCLK4_5_HS
0x11500SCLK4_5_ADLY_ENSCLK4_5_ADLY
0x1160000SCLK4_5_DDLY
0x117CLKout5_FMTCLKout4_FMT
0x118DCLK6_7_DIV[7:0]
0x119DCLK6_7_DDLY[7:0]
0x11ACLKout6_7_PDCLKout6_7_ODLCLKout6_7_IDLDCLK6_7_DDLY_PDDCLK6_7_DDLY[9:8]DCLK6_7_DIV[9:8]
0x11B01CLKout6_SRC_MUXDCLK6_7_PDDCLK6_7_BYPDCLK6_7_DCCDCLK6_7_POLDCLK6_7_HS
0x11C00CLKout7_SRC_MUXSCLK6_7_PDSCLK6_7_DIS_MODESCLK6_7_POLSCLK6_7_HS
0x11D00SCLK6_7_ADLY_ENSCLK6_7_ADLY
0x11E0000SCLK6_7_DDLY
0x11FCLKout7_FMTCLKout6_FMT
0x120DCLK8_9_DIV[7:0]
0x121DCLK8_9_DDLY[7:0]
0x122CLKout8_9_PDCLKout8_9_ODLCLKout8_9_IDLDCLK8_9_DDLY_PDDCLK8_9_DDLY[9:8]DCLK8_9_DIV[9:8]
0x12301CLKout8_SRC_MUXDCLK8_9_PDDCLK8_9_BYPDCLK8_9_DCCDCLK8_9_POLDCLK8_9_HS
0x12400CLKout9_SRC_MUXSCLK8_9_PDSCLK8_9_DIS_MODESCLK8_9_POLSCLK8_9_HS
0x12500SCLK8_9_ADLY_ENSCLK8_9_ADLY
0x1260000SCLK8_9_DDLY
0x127CLKout9_FMTCLKout8_FMT
0x128DCLK10_11_DIV[7:0]
0x129DCLK10_11_DDLY[7:0]
0x12ACLKout10_11_PDCLKout10_11_ODLCLKout10_11_IDLDCLK10_11_DDLY_PDDCLK10_11_DDLY[9:8]DCLK10_11_DIV[9:8]
0x12B01CLKout10_SRC_MUXDCLK10_11_PDDCLK10_11_BYPDCLK10_11_DCCDCLK10_11_POLDCLK10_11_HS
0x12C00CLKout11_SRC_MUXSCLK10_11_PDSCLK10_11_DIS_MODESCLK10_11_POLSCLK10_11_HS
0x12D00SCLK10_11_ADLY_ENSCLK10_11_ADLY
0x12E0000SCLK10_11_DDLY
0x12FCLKout11_FMTCLKout10_FMT
0x130DCLK12_13_DIV[7:0]
0x131DCLK12_13_DDLY[7:0]
0x132CLKout12_13_PDCLKout12_13_ODLCLKout12_13_IDLDCLK12_13_DDLY_PDDCLK12_13_DDLY[9:8]DCLK12_13_DIV[9:8]
0x13301CLKout12_SRC_MUXDCLK12_13_PDDCLK12_13_BYPDCLK12_13_DCCDCLK12_13_POLDCLK12_13_HS
0x13400CLKout13_SRC_MUXSCLK12_13_PDSCLK12_13_DIS_MODESCLK12_13_POLSCLK12_13_HS
0x13500SCLK12_13_ADLY_ENSCLK12_13_ADLY
0x1360000SCLK12_13_DDLY
0x137CLKout13_FMTCLKout12_FMT
0x1380VCO_MUXOSCout_MUXOSCout_FMT
0x139000SYSREF_REQ_ENSYNC_BYPASS0SYSREF_MUX
0x13A000SYSREF_DIV[12:8]
0x13BSYSREF_DIV[7:0]
0x13C000SYSREF_DDLY[12:8]
0x13DSYSREF_DDLY[7:0]
0x13E00000SYSREF_PULSE_CNT
0x13FPLL2_RCLK_
MUX		0PLL2_NCLK_
MUX		PLL1_NCLK_MUXFB_MUXFB_MUX_EN
0x140PLL1_PDVCO_LDO_PDVCO_PDOSCin_PDSYSREF_GBL_PDSYSREF_PDSYSREF_DDLY_PDSYSREF_PLSR_PD
0x141DDLYd_
SYSREF_EN		DDLYd12_ENDDLYd10_ENDDLYd8_ENDDLYd6_ENDDLYd4_ENDDLYd2_ENDDLYd0_EN
0x142DDLYd_STEP_CNT
0x143SYSREF_CLRSYNC_1SHOT_ENSYNC_POLSYNC_ENSYNC_PLL2_
DLD		SYNC_PLL1_
DLD		SYNC_MODE
0x144SYNC_DISSYSREFSYNC_DIS12SYNC_DIS10SYNC_DIS8SYNC_DIS6SYNC_DIS4SYNC_DIS2SYNC_DIS0
0x1452PLL1R_SYNC_ENPLL1R_SYNC_SRCPLL2R_SYNC_ENFIN0_DIV2_ENFIN0_INPUT_TYPE
0x146CLKin_SEL_PIN_ENCLKin_SEL_PIN_POLCLKin2_ENCLKin1_ENCLKin0_ENCLKin2_TYPECLKin1_TYPECLKin0_TYPE
0x147CLKin_SEL_
AUTO_
REVERT_EN		CLKin_SEL_
AUTO_EN		CLKin_SEL_MANUALCLKin1_DEMUXCLKin0_DEMUX
0x14800CLKin_SEL0_MUXCLKin_SEL0_TYPE
0x1490SDIO_RDBK_
TYPE		CLKin_SEL1_MUXCLKin_SEL1_TYPE
0x14A00RESET_MUXRESET_TYPE
0x14BLOS_TIMEOUTLOS_ENTRACK_ENHOLDOVER_
FORCE		MAN_DAC_ENMAN_DAC[9:8]
0x14CMAN_DAC[7:0]
0x14D00DAC_TRIP_LOW
0x14EDAC_CLK_MULTDAC_TRIP_HIGH
0x14FDAC_CLK_CNTR
0x1500CLKin_OVERRIDEHOLDOVER_
EXIT_MODE		HOLDOVER_
PLL1_DET		LOS_EXTERNAL_INPUTHOLDOVER_
VTUNE_DET		CLKin_SWITCH
_CP_TRI		HOLDOVER_
EN
0x15100HOLDOVER_DLD_CNT[13:8]
0x152HOLDOVER_DLD_CNT[7:0]
0x15300CLKin0_R[13:8]
0x154CLKin0_R[7:0]
0x15500CLKin1_R[13:8]
0x156CLKin1_R[7:0]
0x15700CLKin2_R[13:8]
0x158CLKin2_R[7:0]
0x15900PLL1_N[13:8]
0x15APLL1_N[7:0]
0x15BPLL1_WND_SIZEPLL1_CP_TRIPLL1_CP_POLPLL1_CP_GAIN
0x15C00PLL1_DLD_CNT[13:8]
0x15DPLL1_DLD_CNT[7:0]
0x15E000HOLDOVER_EXIT_NADJ
0x15FPLL1_LD_MUXPLL1_LD_TYPE
0x1600000PLL2_R
0x161PLL2_R
0x162PLL2_P0OSCin_FREQPLL2_XTAL_ENPLL2_REF_2X_EN
0x163000000PLL2_N_CAL[17:16]
0x164PLL2_N_CAL[15:8]
0x165PLL2_N_CAL[7:0]
0x166000000PLL2_N[17:16]
0x167PLL2_N[15:8]
0x168PLL2_N[7:0]
0x1690PLL2_WND_SIZEPLL2_CP_GAINPLL2_CP_POLPLL2_CP_TRIPLL2_DLD_EN
0x16A00PLL2_DLD_CNT[13:8]
0x16BPLL2_DLD_CNT[7:0]
0x16C00000000
0x1730PLL2_PRE_PDPLL2_PDFIN0_PD0000
0x177PLL1R_RST
0x182000000CLR_PLL1_LD_LOSTCLR_PLL2_LD_LOST
0x1830000RB_PLL1_DLD_LOSTRB_PLL1_DLDRB_PLL2_DLD_LOSTRB_PLL2_DLD
0x184RB_DAC_VALUE[9:8]RB_CLKin2_
SEL		RB_CLKin1_
SEL		RB_CLKin0_
SEL		RB_CLKin2_
LOS		RB_CLKin1_
LOS		RB_CLKin0_
LOS
0x185RB_DAC_VALUE[7:0]
0x1880XRB_
HOLDOVER		XRB_DAC_RAILRB_DAC_HIGHRB_DAC_LOWRB_DAC_
LOCKED
0x555SPI_LOCK