ZHCSRR7 February 2023 DRV8316C-Q1
PRODUCTION DATA
Table 8-11 lists the memory-mapped registers for the STATUS registers. All register offset addresses not listed in Table 8-11 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0h | IC Status Register | IC Status Register | IC Status Register (Offset = 0h) [Reset = 00h] |
| 1h | Status Register 1 | Status Register 1 | Status Register 1 (Offset = 1h) [Reset = 00h] |
| 2h | Status Register 2 | Status Register 2 | Status Register 2 (Offset = 2h) [Reset = 00h] |
Complex bit access types are encoded to fit into small table cells. Table 8-12 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| R-0 | R -0 | Read Returns 0s |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
IC Status Register is shown in Figure 8-48 and described in Table 8-13.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BK_FLT | SPI_FLT | OCP | NPOR | OVP | OT | FAULT | |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 6 | BK_FLT | R | 0h | Buck Fault Bit
0h = No buck regulator fault condition is detected 1h = Buck regulator fault condition is detected |
| 5 | SPI_FLT | R | 0h | SPI Fault Bit
0h = No SPI fault condition is detected 1h = SPI Fault condition is detected |
| 4 | OCP | R | 0h | Over Current Protection Status Bit
0h = No overcurrent condition is detected 1h = Overcurrent condition is detected |
| 3 | NPOR | R | 0h | Supply Power On Reset Bit
0h = Power on reset condition is detected on VM 1h = No power-on-reset condition is detected on VM |
| 2 | OVP | R | 0h | Supply Overvoltage Protection Status Bit
0h = No overvoltage condition is detected on VM 1h = Overvoltage condition is detected on VM |
| 1 | OT | R | 0h | Overtemperature Fault Status Bit
0h = No overtemperature warning / shutdown is detected 1h = Overtemperature warning / shutdown is detected |
| 0 | FAULT | R | 0h | Device Fault Bit
0h = No fault condition is detected 1h = Fault condition is detected |
Status Register 1 is shown in Figure 8-49 and described in Table 8-14.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OTW | OTS | OCP_HC | OCL_LC | OCP_HB | OCP_LB | OCP_HA | OCP_LA |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | OTW | R | 0h | Overtemperature Warning Status Bit
0h = No overtemperature warning is detected 1h = Overtemperature warning is detected |
| 6 | OTS | R | 0h | Overtemperature Shutdown Status Bit
0h = No overtemperature shutdown is detected 1h = Overtemperature shutdown is detected |
| 5 | OCP_HC | R | 0h | Overcurrent Status on High-side switch of OUTC
0h = No overcurrent detected on high-side switch of OUTC 1h = Overcurrent detected on high-side switch of OUTC |
| 4 | OCL_LC | R | 0h | Overcurrent Status on Low-side switch of OUTC
0h = No overcurrent detected on low-side switch of OUTC 1h = Overcurrent detected on low-side switch of OUTC |
| 3 | OCP_HB | R | 0h | Overcurrent Status on High-side switch of OUTB
0h = No overcurrent detected on high-side switch of OUTB 1h = Overcurrent detected on high-side switch of OUTB |
| 2 | OCP_LB | R | 0h | Overcurrent Status on Low-side switch of OUTB
0h = No overcurrent detected on low-side switch of OUTB 1h = Overcurrent detected on low-side switch of OUTB |
| 1 | OCP_HA | R | 0h | Overcurrent Status on High-side switch of OUTA
0h = No overcurrent detected on high-side switch of OUTA 1h = Overcurrent detected on high-side switch of OUTA |
| 0 | OCP_LA | R | 0h | Overcurrent Status on Low-side switch of OUTA
0h = No overcurrent detected on low-side switch of OUTA 1h = Overcurrent detected on low-side switch of OUTA |
Status Register 2 is shown in Figure 8-50 and described in Table 8-15.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | OTP_ERR | BUCK_OCP | BUCK_UV | VCP_UV | SPI_PARITY | SPI_SCLK_FLT | SPI_ADDR_FLT |
| R-0-0h | R-0h | R-0h | R-0h | R-0h | R-0-0h | R-0h | R-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R-0 | 0h | Reserved |
| 6 | OTP_ERR | R | 0h | One Time Programmabilty Error
0h = No OTP error is detected 1h = OTP Error is detected |
| 5 | BUCK_OCP | R | 0h | Buck Regulator Overcurrent Staus Bit
0h = No buck regulator overcurrent is detected 1h = Buck regulator overcurrent is detected |
| 4 | BUCK_UV | R | 0h | Buck Regulator Undervoltage Staus Bit
0h = No buck regulator undervoltage is detected 1h = Buck regulator undervoltage is detected |
| 3 | VCP_UV | R | 0h | Charge Pump Undervoltage Status Bit
0h = No charge pump undervoltage is detected 1h = Charge pump undervoltage is detected |
| 2 | SPI_PARITY | R-0 | 0h | SPI Parity Error Bit
0h = No SPI parity error is detected 1h = SPI parity error is detected |
| 1 | SPI_SCLK_FLT | R | 0h | SPI Clock Framing Error Bit
0h = No SPI clock framing error is detected 1h = SPI clock framing error is detected |
| 0 | SPI_ADDR_FLT | R | 0h | SPI Address Error Bit
0h = No SPI address fault is detected (due to accessing non-user register) 1h = SPI address fault is detected |