ZHCSI19F April 2010 – April 2018 DLPC200
Details about the chip power-up requirements are included in the DLPZ004 chipset data sheet. For the DLPC200, there is a 50-MHz reference clock that must meet the specifications listed in Table 8. Additionally, at power-up, the 3.3-V supply must be stable for 2 s before the global reset (RESET) occurs, and then PWR_GOOD occurs within 20 ms.
|PART NUMBER||FREQUENCY STABILITY||FREQUENCY||SUPPLY VOLTAGE|
|ASV-50.000MHZ-E-J-T||±20 ppm (0.002% or ±0.001 MHz)||50 MHz||3.3 V|