ZHCSI19F April   2010  – April 2018 DLPC200

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
    2.     Power and Ground Pins
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  I/O Electrical Characteristics
    6. 6.6  Video Input Pixel Interface Timing Requirements
    7. 6.7  I2C Interface Timing Requirements
    8. 6.8  USB Read Interface Timing Requirements
    9. 6.9  USB Write Interface Timing Requirements
    10. 6.10 SPI Slave Interface Timing Requirements
    11. 6.11 Parallel Flash Interface Timing Requirements
    12. 6.12 Serial Flash Interface Timing Requirements
    13. 6.13 Static RAM Interface Timing Requirements
    14. 6.14 DMD Interface Timing Requirements
    15. 6.15 DLPA200 Interface Timing Requirements
    16. 6.16 DDR2 SDR Memory Interface Timing Requirements
    17. 6.17 Video Input Pixel Interface – Image Sync and Blanking Requirements
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Frame Rates
    4. 7.4 Device Functional Modes
      1. 7.4.1 Video Modes
      2. 7.4.2 Structured Light Modes
        1. 7.4.2.1 Static Image Buffer Mode
        2. 7.4.2.2 Real Time Structured Light Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 DLPC200 System Interfaces
          1. 8.2.2.1.1  DLPC200 Master, I2C Interface for EDID Programming
          2. 8.2.2.1.2  USB Interface
          3. 8.2.2.1.3  Bus Protocol
          4. 8.2.2.1.4  SPI Slave Interface
          5. 8.2.2.1.5  Parallel Flash Memory Interface
          6. 8.2.2.1.6  Serial Flash Memory Interface
          7. 8.2.2.1.7  SRAM Interface
          8. 8.2.2.1.8  DDR2 SDR Memory Interface
          9. 8.2.2.1.9  Projector Image and Control Port Signals
          10. 8.2.2.1.10 SDRAM Memory
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
    1. 9.1 Power-Up Requirements
    2. 9.2 Power-Down Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Impedance Requirements
      2. 10.1.2 PCB Signal Routing
      3. 10.1.3 Fiducials
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Heat Sink
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 器件标记
    2. 11.2 文档支持
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Parallel Flash Memory Interface

The controller parallel flash memory interface supports a high-speed NOR device with a 16-bit data bus and up to 1 GB of memory.

To perform an asynchronous read, an address is driven onto the address bus, and CE is asserted. WE and RST must already have been deasserted. WAIT is configured to be active low and is set to a deasserted state. ADV must be held low throughout the read cycle. CLK is not used for asynchronous reads and is ignored. After OE is asserted, the data is driven onto DQ[15:0] after an initial access time tAVQV or tGLQV delay.

The WAIT signal indicates data valid when the device is operating in asynchronous mode (RCR.15 = 0). The WAIT signal is only deasserted when data is valid on the bus. When the device is operating in asynchronous non-array read mode, such as read status, read ID, or read query, the WAIT signal is also deasserted when data is valid on the bus. WAIT behavior during asynchronous non-array reads at the end of the word line works correctly only on the first data access.

To perform a write operation, both CE and WE are asserted while RST and OE are deasserted. During a write operation, address and data are latched on the rising edge of WE or CE, whichever occurs first. When the device is operating in write operations, WAIT is set to a deasserted state as determined by RCR.10.

Table 4. Recommended Parallel Flash Devices

PART NUMBER MANUFACTURER SIZE
JS28F00AP30BF Numonyx 128 Mb