ZHCSN14H June 2005 – June 2025 ADS1232 , ADS1234
PRODUCTION DATA
| PIN | TYPE | DESCRIPTION | ||||||
|---|---|---|---|---|---|---|---|---|
| NAME | ADS1232 | ADS1234 | ||||||
| A0 | 8 | 8 | Digital input | Input MUX select pins. See Table 7-1 and Table 7-2 for more information. | ||||
| A1 | — | 7 | Digital input | Input MUX select pins. See Table 7-1 and Table 7-2 for more information. | ||||
| AGND | 17 | 21 | Analog | Analog ground | ||||
| AINN1 | 12 | 12 | Analog input | Negative analog input channel 1 | ||||
| AINN2 | 13 | 17 | Analog input | Negative analog input channel 2 | ||||
| AINN3 | — | 14 | Analog input | Negative analog input channel 3 | ||||
| AINN4 | — | 15 | Analog input | Negative analog input channel 4 | ||||
| AINP1 | 11 | 11 | Analog input | Positive analog input channel 1 | ||||
| AINP2 | 14 | 18 | Analog input | Positive analog input channel 2 | ||||
| AINP3 | — | 13 | Analog input | Positive analog input channel 3 | ||||
| AINP4 | — | 16 | Analog input | Positive analog input channel 4 | ||||
| AVDD | 18 | 22 | Analog | Analog power supply: 2.7V to 5.3V | ||||
| CAP | 9, 10 | 9, 10 | Analog | PGA bypass, connect a 0.1µF capacitor across pins 9 and 10 | ||||
| CLKIN/XTAL1 | 3 | 3 | Digital input | External crystal connection 1, or external clock input, or tie low to activate internal oscillator. See the Clock Sources section for more information. | ||||
| DGND | 2, 5, 6 | 2, 5, 6 | Digital | Digital ground | ||||
| DRDY/DOUT | 24 | 28 | Digital output | Dual-purpose output: Data ready indicates valid data by going low. Data output outputs data, MSB first, on the first rising edge of SCLK. |
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| DVDD | 1 | 1 | Digital | Digital power supply: 2.7V to 5.3V | ||||
| GAIN0 | 19 | 23 | Digital input | Gain select pins. See the Low-Noise PGA section for more information. | ||||
| GAIN1 | 20 | 24 | Digital input | Gain select pins. See the Low-Noise PGA section for more information. | ||||
| REFN | 15 | 19 | Analog input | Negative reference input | ||||
| REFP | 16 | 20 | Analog input | Positive reference input | ||||
| PDWN | 22 | 26 | Digital input | Power-down: hold this pin low to power down and reset the ADC. Toggle the pin at device power-up. See the Power-Up Sequence section for more information. | ||||
| SCLK | 23 | 27 | Digital input | Serial clock: clock out data on the rising edge. Also used to initiate offset calibration and standby modes. See the Offset Calibration Mode and Standby Mode With Offset-Calibration sections for more information. | ||||
| SPEED | 21 | 25 | Digital input | Data rate select. See the Data Rate section for more information. | ||||
| TEMP | 7 | — | Digital input | Temperature sensor select. See Table 7-1 for more information. | ||||
| XTAL2 | 4 | 4 | Digital | External crystal connection 2 | ||||