ZHCSN14H June   2005  – June 2025 ADS1232 , ADS1234

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs (AINPX, AINNX)
      2. 7.3.2  Temperature Sensor (ADS1232 Only)
      3. 7.3.3  Low-Noise PGA
        1. 7.3.3.1 PGA Bypass Capacitor
      4. 7.3.4  Voltage Reference Inputs (REFP, REFN)
      5. 7.3.5  Clock Sources
      6. 7.3.6  Digital Filter Frequency Response
      7. 7.3.7  Settling Time
      8. 7.3.8  Data Rate
      9. 7.3.9  Data Format
      10. 7.3.10 Data Ready and Data Output (DRDY/DOUT)
      11. 7.3.11 Serial Clock Input (SCLK)
      12. 7.3.12 Data Retrieval
    4. 7.4 Device Functional Modes
      1. 7.4.1 Offset Calibration Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Standby Mode With Offset-Calibration
      4. 7.4.4 Power-Down Mode
      5. 7.4.5 Power-Up Sequence
      6. 7.4.6 Summary of Serial Interface Waveforms
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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7.3.8 Data Rate

The ADS123x data rate is set by the SPEED pin, as shown in Table 7-6. When SPEED is low, the data rate is nominally 10 SPS. This data rate provides the lowest noise, and also has excellent rejection of both 50-Hz and 60-Hz line-cycle interference. For applications requiring fast data rates, setting SPEED high selects a data rate of 80 SPS.

Table 7-6 Data Rate Settings
SPEED
PIN		 DATA RATE
INTERNAL OSCILLATOR
OR 4.9152-MHz CRYSTAL		 EXTERNAL
OSCILLATOR
0 10 SPS fCLK / 491,520
1 80 SPS fCLK / 61,440