ZHCSN14H June   2005  – June 2025 ADS1232 , ADS1234

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs (AINPX, AINNX)
      2. 7.3.2  Temperature Sensor (ADS1232 Only)
      3. 7.3.3  Low-Noise PGA
        1. 7.3.3.1 PGA Bypass Capacitor
      4. 7.3.4  Voltage Reference Inputs (REFP, REFN)
      5. 7.3.5  Clock Sources
      6. 7.3.6  Digital Filter Frequency Response
      7. 7.3.7  Settling Time
      8. 7.3.8  Data Rate
      9. 7.3.9  Data Format
      10. 7.3.10 Data Ready and Data Output (DRDY/DOUT)
      11. 7.3.11 Serial Clock Input (SCLK)
      12. 7.3.12 Data Retrieval
    4. 7.4 Device Functional Modes
      1. 7.4.1 Offset Calibration Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Standby Mode With Offset-Calibration
      4. 7.4.4 Power-Down Mode
      5. 7.4.5 Power-Up Sequence
      6. 7.4.6 Summary of Serial Interface Waveforms
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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6.1 Noise Performance

The ADS123x offer outstanding noise performance that can be optimized for a given full-scale range using the programmable gain amplifier (PGA). AVDD = 5V, VREF = 5V, Data Rate = 10SPS through AVDD = 3V, VREF = 3V, Data Rate = 80SPS summarize the typical noise performance with inputs shorted externally for different gains, data rates, and voltage reference values. The RMS and peak-to-peak noise data are referred to the input.

The effective resolution of the ADC is defined as:

Equation 1. Effective Resolution (Bits) = ln (FSR / RMS Noise) / ln (2)

The noise-free resolution of the ADC is defined as:

Equation 2. Noise-Free Resolution (Bits)= ln (FSR / Peak-to-Peak Noise) / ln (2)

where

  • FSR = full-scale range = VREF / gain
Table 6-1 AVDD = 5V, VREF = 5V, Data Rate = 10SPS
GAIN RMS NOISE PEAK-TO-PEAK NOISE(1) EFFECTIVE RESOLUTION (Bits) NOISE-FREE RESOLUTION (Bits)
1 420nV 1.79µV 23.5 21.4
2 270nV 900nV 23.1 21.4
64 19nV 125nV 22.0 19.2
128 17nV 110nV 21.1 18.4
(1) Peak-to-peak noise data are based on direct measurement.
Table 6-2 AVDD = 5V, VREF = 5V, Data Rate = 80SPS
GAIN RMS NOISE PEAK-TO-PEAK NOISE(1) EFFECTIVE RESOLUTION (Bits) NOISE-FREE RESOLUTION (Bits)
1 1.36µV 8.3µV 21.8 19.2
2 850nV 5.5µV 21.5 18.8
64 48nV 307nV 20.6 18
128 44nV 247nV 19.7 17.2
(1) Peak-to-peak noise data are based on direct measurement.
Table 6-3 AVDD = 3V, VREF = 3V, Data Rate = 10SPS
GAIN RMS NOISE PEAK-TO-PEAK NOISE(1) EFFECTIVE RESOLUTION (Bits) NOISE-FREE RESOLUTION (Bits)
1 450nV 2.8µV 22.6 20
2 325nV 1.8µV 22.1 19.7
64 20nV 130nV 21.2 18.5
128 18nV 115nV 20.3 17.6
(1) Peak-to-peak noise data are based on direct measurement.
Table 6-4 AVDD = 3V, VREF = 3V, Data Rate = 80SPS
GAIN RMS NOISE PEAK-TO-PEAK NOISE(1) EFFECTIVE RESOLUTION (Bits) NOISE-FREE RESOLUTION (Bits)
1 2.2µV 12µV 20.4 17.9
2 1.2µV 6.8µV 20.2 17.8
64 54nV 340nV 19.7 17.1
128 48nV 254nV 18.9 16.5
(1) Peak-to-peak noise data are based on direct measurement of 1024 samples.