ZHCSN14H June   2005  – June 2025 ADS1232 , ADS1234

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs (AINPX, AINNX)
      2. 7.3.2  Temperature Sensor (ADS1232 Only)
      3. 7.3.3  Low-Noise PGA
        1. 7.3.3.1 PGA Bypass Capacitor
      4. 7.3.4  Voltage Reference Inputs (REFP, REFN)
      5. 7.3.5  Clock Sources
      6. 7.3.6  Digital Filter Frequency Response
      7. 7.3.7  Settling Time
      8. 7.3.8  Data Rate
      9. 7.3.9  Data Format
      10. 7.3.10 Data Ready and Data Output (DRDY/DOUT)
      11. 7.3.11 Serial Clock Input (SCLK)
      12. 7.3.12 Data Retrieval
    4. 7.4 Device Functional Modes
      1. 7.4.1 Offset Calibration Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Standby Mode With Offset-Calibration
      4. 7.4.4 Power-Down Mode
      5. 7.4.5 Power-Up Sequence
      6. 7.4.6 Summary of Serial Interface Waveforms
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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5.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +105°C; typical specifications are at TA = 25°C; all specifications are at AVDD = DVDD = V(REFP) = 5V, V(REFN) = AGND, and fCLK = 4.9152MHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Differential input current Gain = 1 ±3 nA
Gain = 2 ±6
Gain = 64, 128 ±3.5
SYSTEM PERFORMANCE
Resolution No missing codes 24 Bits
fDATA Data rate Internal oscillator, SPEED = high 78 80 82.4 SPS
Internal oscillator, SPEED = low 9.75 10 10.3
External oscillator, SPEED = high fCLK / 61,440
External oscillator, SPEED = low fCLK / 491,520
Digital filter settling time Full settling, readings synchronized with A0, A1 pins 4 Conversions
INL Integral nonlinearity Differential input, end-point fit, gain = 1, 2 –0.001 ±0.0002 0.001 % of FSR(1)
Differential input, end-point fit, gain = 64, 128 ±0.0004
Input offset error(2) Gain = 1 –5 ±0.2 5 ppm of FS
Gain = 128 –1 ±0.02 1
Input offset drift Gain = 1 ±0.3 µV/°C
Gain = 128 ±10 nV/°C
Gain error(3) Gain = 1 –0.02 ±0.001 0.02 %
Gain = 128 –0.1 ±0.01 0.1
Gain drift Gain = 1 ±0.2 ppm/°C
Gain = 128 ±2.5
NMRR Normal-mode rejection ratio (4) Internal oscillator, fDATA = 10SPS
fIN = 50Hz or 60Hz, ±1Hz		 100 110 dB
External oscillator, fDATA = 10SPS
fIN = 50Hz or 60Hz, ±1Hz		 120 130
CMRR Common-mode rejection ratio At DC, gain = 1, ΔV = 1V, VCM = AVDD / 2 95 110 dB
At DC, gain = 128, ΔV = 0.1V, VCM = AVDD / 2 95 110
en Input-referred noise See the Noise Performance section
PSRR Power-supply rejection AVDD, at DC, gain = 1, ΔV = 1V 85 dB
AVDD, at DC, gain = 128, ΔV = 0.1V 100 120
VOLTAGE REFERENCE INPUT
Input current 10 nA
DIGITAL LOGIC LEVELS
VIH High-level input voltage 0.7 DVDD V
VIL Low-level input voltage 0.2 DVDD V
VOH High-level output voltage IOH = 1mA DVDD – 0.4 V
VOL Low-level output voltage IOL = 1mA 0.2 DVDD V
Input leakage current 0V < VIN < DVDD –10 10 µA
POWER SUPPLY
I(AVDD) Analog supply current Normal mode, AVDD = 3V, gain = 1, 2 600 1300 µA
Normal mode, AVDD = 3V, gain = 64, 128 1350 2500
Normal mode, AVDD = 5V, gain = 1, 2 650 1300
Normal mode, AVDD = 5V, gain = 64, 128 1350 2500
Standby mode 0.1 1
Power-down 0.1 1
I(DVDD) Digital supply current Normal mode, DVDD = 3V, gain = 1, 2 60 95 µA
Normal mode, DVDD = 3V, gain = 64, 128 75 120
Normal mode, DVDD = 5V, gain = 1, 2 95 130
Normal mode, DVDD = 5V, gain = 64, 128 75 120
Standby mode, SCLK = high, DVDD = 3V 45 80
Standby mode, SCLK = high, DVDD = 5V 65 80
Power-down 0.2 1.3
PD Power dissipation, total Normal mode, AVDD = DVDD = 3V, gain = 1, 2 2 4.2 mW
Normal mode, AVDD = DVDD = 5V, gain = 1, 2 3.7 7.2
Normal mode, AVDD = DVDD = 3V, gain = 64, 128 4.3 7.9
Normal mode, AVDD = DVDD = 5V, gain = 64, 128 7.1 13.1
Standby mode, AVDD = DVDD = 5V 0.3 0.4
(1) FSR = full-scale range = VREF / Gain.
(2) Input offset error specified after calibration. Recalibration minimizes these errors to the level of noise at any temperature.
(3) Gain errors are calibrated at the factory (AVDD = 5V, all gains, TA = 25°C).
(4) Specification is verified by the combination of design and final production test.