ZHCSKL4 December 2019 ADC3421-Q1
PRODUCTION DATA.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HIGH IF MODE<7:6> | 0 | 0 | 0 | 0 | 0 | 0 | |
| W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
| LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | HIGH IF MODE<7:6> | R/W | 0h | Set all register bits belonging to HIGH IF MODE as logic HIGH to improve HD3 by a couple of dB for IF > 100 MHz. |
| 5-0 | 0 | W | 0h | Must write 0. |