ZHCSKL4 December 2019 ADC3421-Q1
PRODUCTION DATA.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CHA PDN | CHB PDN | CHC PDN | CHD PDN | STANDBY | GLOBAL PDN | 0 | CONFIG PDN PIN |
| W-0h | R/W-0h | R/W-0h | W-0h | R/W-0h | R/W-0h | W-0h | R/W-0h |
| LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | CHA PDN | W | 0h | 0 = Normal operation
1 = Power-down channel A |
| 6 | CHB PDN | R/W | 0h | 0 = Normal operation
1 = Power-down channel B |
| 5 | CHC PDN | R/W | 0h | 0 = Normal operation
1 = Power-down channel C |
| 4 | CHD PDN | W | 0h | 0 = Normal operation
1 = Power-down channel D |
| 3 | STANDBY | R/W | 0h | The ADCs of both channels enter standby.
0 = Normal operation 1 = Standby |
| 2 | GLOBAL PDN | R/W | 0h | 0 = Normal operation
1 = Global power-down |
| 1 | 0 | W | 0h | Must write 0. |
| 0 | CONFIG PDN PIN | R/W | 0h | This bit configures the PDN pin as either a global power-down or standby pin.
0 = Logic high voltage on the PDN pin sends the device into global power-down 1 = Logic high voltage on the PDN pin sends the device into standby |