ZHCSKL4 December   2019 ADC3421-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      10MHz IF 时的频谱（SFDR = 90dBc，SNR = 71.2dBFS，SINAD = 71.1dBFS，THD = 89dBc）
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: General
    6. 6.6  Electrical Characteristics: AC Performance
    7. 6.7  Digital Characteristics
    8. 6.8  Timing Requirements: General
    9. 6.9  Timing Requirements: LVDS Output
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Timing Diagrams
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
      2. 8.3.2 Clock Input
        1. 8.3.2.1 SNR and Clock Jitter
      3. 8.3.3 Digital Output Interface
        1. 8.3.3.1 One-Wire Interface: 12x Serialization
        2. 8.3.3.2 Two-Wire Interface: 6x Serialization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Input Clock Divider
      2. 8.4.2 Chopper Functionality
      3. 8.4.3 Power-Down Control
      4. 8.4.4 Internal Dither Algorithm
      5. 8.4.5 Summary of Performance Mode Registers
      6. 8.4.6 Device Diagnostic Modes
        1. 8.4.6.1 Internal Reference and Clock Status Check
        2. 8.4.6.2 DC Input check
        3. 8.4.6.3 Mean and Variance Measurement
        4. 8.4.6.4 Temperature Sensor
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Register Initialization
          1. 8.5.1.1.1 Serial Register Write
          2. 8.5.1.1.2 Serial Register Readout
      2. 8.5.2 Register Initialization
    6. 8.6 Register Maps
      1. 8.6.1 Serial Register Description
        1. 8.6.1.1  Register 01h (address = 01h)
          1. Table 7. Register 01h Field Descriptions
        2. 8.6.1.2  Register 02h (address = 02h)
          1. Table 8. Register 02h Field Descriptions
        3. 8.6.1.3  Register 03h (address = 03h)
          1. Table 9. Register 03h Field Descriptions
        4. 8.6.1.4  Register 04h (address = 04h)
          1. Table 10. Register 04h Field Descriptions
        5. 8.6.1.5  Register 05h (address = 05h)
          1. Table 11. Register 05h Field Descriptions
        6. 8.6.1.6  Register 06h (address = 06h)
          1. Table 12. Register 06h Field Descriptions
        7. 8.6.1.7  Register 07h (address = 07h)
          1. Table 13. Register 07h Field Descriptions
        8. 8.6.1.8  Register 09h (address = 09h)
          1. Table 14. Register 09h Field Descriptions
        9. 8.6.1.9  Register 0Ah (address = 0Ah)
          1. Table 15. Register 0Ah Field Descriptions
        10. 8.6.1.10 Register 0Bh (address = 0Bh)
          1. Table 16. Register 0Bh Field Descriptions
        11. 8.6.1.11 Register 0Eh (address = 0Eh)
          1. Table 17. Register 0Eh Field Descriptions
        12. 8.6.1.12 Register 0Fh (address = 0Fh)
          1. Table 18. Register 0Fh Field Descriptions
        13. 8.6.1.13 Register 10h (address = 10h)
          1. Table 19. Register 10h Field Descriptions
        14. 8.6.1.14 Register 11h (address = 11h)
          1. Table 20. Register 11h Field Descriptions
        15. 8.6.1.15 Register 13h (address = 13h)
          1. Table 21. Register 13h Field Descriptions
        16. 8.6.1.16 Register 14h (address = 14h)
          1. Table 23. Register 14h Field Descriptions
        17. 8.6.1.17 Register 15h (address = 15h)
          1. Table 24. Register 15h Field Descriptions
        18. 8.6.1.18 Register 16h (address = 16h)
          1. Table 25. Register 16h Field Descriptions
        19. 8.6.1.19 Register 17h (address = 17h)
          1. Table 26. Register 17h Field Descriptions
        20. 8.6.1.20 Register 18h (address = 18h)
          1. Table 27. Register 18h Field Descriptions
        21. 8.6.1.21 Register 19h (address = 19h)
          1. Table 28. Register 19h Field Descriptions
        22. 8.6.1.22 Register 25h (address = 25h)
          1. Table 29. Register 25h Field Descriptions
        23. 8.6.1.23 Register 27h (address = 27h)
          1. Table 30. Register 27h Field Descriptions
        24. 8.6.1.24 Register 4Bh (address = 4Bh)
          1. Table 31. Register 4Bh Field Descriptions
        25. 8.6.1.25 Register 11Dh (address = 11Dh)
          1. Table 32. Register 11Dh Field Descriptions
        26. 8.6.1.26 Register 122h (address = 122h)
          1. Table 33. Register 122h Field Descriptions
        27. 8.6.1.27 Register 134h (address = 134h)
          1. Table 34. Register 134h Field Descriptions
        28. 8.6.1.28 Register 139h (address = 139h)
          1. Table 35. Register 139h Field Descriptions
        29. 8.6.1.29 Register 21Dh (address = 21Dh)
          1. Table 36. Register 21Dh Field Descriptions
        30. 8.6.1.30 Register 222h (address = 222h)
          1. Table 37. Register 222h Field Descriptions
        31. 8.6.1.31 Register 234h (address = 234h)
          1. Table 38. Register 234h Field Descriptions
        32. 8.6.1.32 Register 239h (address = 239h)
          1. Table 39. Register 239h Field Descriptions
        33. 8.6.1.33 Register 308h (address = 308h)
          1. Table 40. Register 308h Field Descriptions
        34. 8.6.1.34 Register 31Dh (address = 31Dh)
          1. Table 41. Register 31Dh Field Descriptions
        35. 8.6.1.35 Register 41Dh (address = 41Dh)
          1. Table 42. Register 41Dh Field Descriptions
        36. 8.6.1.36 Register 422h (address = 422h)
          1. Table 43. Register 422h Field Descriptions
        37. 8.6.1.37 Register 434h (address = 434h)
          1. Table 44. Register 434h Field Descriptions
        38. 8.6.1.38 Register 439h (address = 439h)
          1. Table 45. Register 439h Field Descriptions
        39. 8.6.1.39 Register 51Dh (address = 51Dh)
          1. Table 46. Register 51Dh Field Descriptions
        40. 8.6.1.40 Register 522h (address = 522h)
          1. Table 47. Register 522h Field Descriptions
        41. 8.6.1.41 Register 534h (address = 534h)
          1. Table 48. Register 534h Field Descriptions
        42. 8.6.1.42 Register 539h (address = 539h)
          1. Table 49. Register 539h Field Descriptions
        43. 8.6.1.43 Register 608h (address = 608h)
          1. Table 50. Register 608h Field Descriptions
        44. 8.6.1.44 Register 61Dh (address = 61Dh)
          1. Table 51. Register 61Dh Field Descriptions
        45. 8.6.1.45 Register 70Ah (address = 70Ah)
          1. Table 52. Register 70Ah Field Descriptions
        46. 8.6.1.46 Register 71Ah (address = 71Ah)
          1. Table 53. Register 71Ah Field Descriptions
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Driving Circuit Design: Low Input Frequencies
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
      3. 9.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.2 Clock Input

The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 0.95 V using internal 5-kΩ resistors. The self-bias clock inputs of the ADC3421-Q1 can be driven by the transformer-coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in Figure 36, Figure 37, and Figure 38. See Figure 39 for details regarding the internal clock buffer.

ADC3421-Q1 ai_dif_sinewave_clk_bas550.gif
NOTE: RT = termination resistor, if necessary.
Figure 36. Differential Sine-Wave Clock Driving Circuit
ADC3421-Q1 ai_lvds_clk_drv_bas550.gifFigure 37. LVDS Clock Driving Circuit
ADC3421-Q1 ai_lvpecl_clk_drv_bas550.gifFigure 38. LVPECL Clock Driving Circuit
ADC3421-Q1 ai_intclk_buffer_sbas670.gif
NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.
Figure 39. Internal Clock Buffer

A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 40. However, for best performance the clock inputs must be driven differentially, thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input.

ADC3421-Q1 ai_drv_cir_1end_las900.gifFigure 40. Single-Ended Clock Driving Circuit