TIDUCL3 February   2017

 

  1. 1 Overview
  2. 2 Resources
  3. 3 Features
  4. 4 Applications
  5. 5 Design Images
  6. 6 System Overview
    1. 6.1 System Description
    2. 6.2 Key System Specifications
    3. 6.3 Block Diagram
    4. 6.4 Highlighted Products
      1. 6.4.1 LMT87-Q1
      2. 6.4.2 TLC555-Q1
      3. 6.4.3 OPA2377-Q1
      4. 6.4.4 TL431-Q1
      5. 6.4.5 TPS92691-Q1
  7. 7 System Design Theory
    1. 7.1  PCB and Form Factor
    2. 7.2  Optimizing Board Performance Based on LED String Voltage and Current
    3. 7.3  Switching Frequency
    4. 7.4  Output Overvoltage Protection (OVP)
    5. 7.5  Current Monitoring (IMON)
    6. 7.6  Thermal Foldback
      1. 7.6.1 Changing Thermal Foldback Response
        1. 7.6.1.1 Changing Starting Point for Thermal Foldback
        2. 7.6.1.2 Changing Slope of Thermal Foldback
        3. 7.6.1.3 Constant Current at High Temperatures
      2. 7.6.2 Thermal Foldback Without PWM Dimming
    7. 7.7  Clock Generation (PWM)
    8. 7.8  Onboard Supply and Setting Duty Cycle
    9. 7.9  Buffering, Averaging, and Filtering
    10. 7.10 Boost Converter
  8. 8 Getting Started Hardware
    1. 8.1 Hardware
    2. 8.2 LED Selection
    3. 8.3 J3, LED+, LED– (Boost)
    4. 8.4 J1, POS(+), NEG(–)
    5. 8.5 J4, Temperature Sensor Connection
    6. 8.6 Duty Cycle Adjust
  9. 9 Testing and Results
    1. 9.1 Duty Cycle Accuracy
    2. 9.2 Thermal Foldback Testing
    3. 9.3 EMI Testing
    4. 9.4 Accuracy Calculation
  10. 10Design Files
    1. 10.1 Schematics
    2. 10.2 Bill of Materials
    3. 10.3 PCB Layout Recommendations
      1. 10.3.1 Layout Prints
    4. 10.4 Altium Project
    5. 10.5 Gerber Files
    6. 10.6 Assembly Drawings
  11. 11Related Documentation
    1. 11.1 Trademarks
  12. 12About the Author

7.7 Clock Generation (PWM)

Connecting TRIG to THRES, as Figure 17 shows, causes the timer to run as a multivibrator. The capacitor C1 charges through R1 and D1 to the threshold voltage level (approximately 0.67 VDD) and then discharges through R2 only to the value of the trigger voltage level (approximately 0.33 VDD). As Figure 18 shows, the output is high during the charging cycle (tc(H)) and low during the discharge cycle (tc(L)).

TIDA-01382 tlc555-q1-clock-generation.gifFigure 17. TLC555-Q1 Clock Generation
TIDA-01382 TLC555-Trigger-W.gifFigure 18. Trigger and Threshold Voltage Waveform

The values of R1, D1, R2, and C1 control the duty cycle, as the following equations show:

TIDA-01382 EQ_01_TIDUC97.gif
TIDA-01382 EQ_01_Part_2_TIDUC97.gif
TIDA-01382 tida-01382-equation-period.gif
Equation 16. TIDA-01382 tida-01382-equation-output-waveform.gif

  • tc(H) = 100 nF × 10 kΩ × ln 2 = 693 µs
  • tc(L) = 100 nF × 39 kΩ × ln 2 = 2.7 ms
  • Period = tc(H) + tc(L) = 3.39 ms
  • Output waveform duty cycle = 20.4%

The preceding formulas do not allow for any propagation delay times from the TRIG and THRES inputs to DISCH. These delay times add directly to the period and create differences between calculated and actual values that increase with frequency. In addition, the internal ON-state resistance (rON) during discharge adds to R2 to provide another source of timing error in the calculation when R2 is very low or rON is very high. These errors can be canceled out by applying a feedback loop.