ZHCSMQ0I october   2004  – may 2023 TPS715-Q1

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4.     Thermal Information
    5. 6.4 Electrical Characteristics
    6. 6.5 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Wide Supply Range
      2. 7.3.2 Low Quiescent Current
      3. 7.3.3 Dropout Voltage (VDO)
      4. 7.3.4 Current Limit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1 Programming the TPS71501-Q1 Adjustable LDO Regulator
        2. 8.2.1.2 External Capacitor Requirements
        3. 8.2.1.3 Input and Output Capacitor Requirements
        4. 8.2.1.4 Reverse Current
        5. 8.2.1.5 Feed-Forward Capacitor (CFF)
        6. 8.2.1.6 Power Dissipation (PD)
        7. 8.2.1.7 Estimating Junction Temperature
      2. 8.2.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Power Dissipation
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Module
        2. 9.1.1.2 Spice Models
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 接收文档更新通知
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 静电放电警告
    7. 9.7 术语表
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DCK|5
散热焊盘机械数据 (封装 | 引脚)
订购信息

Application Curves

Figure 8-5 illustrates the input voltage ramp from 0 V to just below 24 V (CH1), the 3.3-V regulated output voltage (CH3), and the 50-mA output current (CH4). The scale on CH4 is 50 mA/div.

Figure 8-6 illustrates the input voltage ramp from 0 V to 8 V, the 3.3-V regulated output voltage, and the 50-mA output current.

Figure 8-7 illustrates the load transient waveform of the TPS71533-Q1, output current is switched between 0 mA and 50 mA (CH4). Input voltage is set at 4.3 V (CH1). Output voltage DC (CH3) and output voltage AC (CH2) are also illustrated in the waveform.

Figure 8-8 illustrates the load transient waveform of the TPS71533-Q1, output current is switched between 0 mA and 50 mA with a slew rate of 0.5 A/μs. Input voltage is set at 4.3 V. Output voltage AC is illustrated in the waveform to capture the undershoot and overshoot behavior.

Figure 8-9 illustrates the line transient waveform of the TPS71533-Q1, where input voltage is switched between 5 V and 14 V with slew rate of 0.66 V/μs. Load current is set at 50 mA. Output voltage AC is illustrated in the waveform to capture the undershoot and overshoot behavior.

Figure 8-10 illustrates the fast dropout exit waveform of the TPS71533-Q1, where input voltage is switched between 2.5 V and 14 V with slew rate of 1.15 V/μs. Load current is set at 1 mA and 50 mA. Output voltage AC is illustrated in the waveform to capture the undershoot and overshoot behavior.

GUID-BD262FBD-F49C-405E-98C9-4CA74B72AC43-low.pngFigure 8-5 TPS71533-Q1 Power-Up and Power-Down Waveform for Legacy Chip
GUID-33471840-705E-4D07-9AE6-4C5AB6C24A90-low.pngFigure 8-7 TPS71533-Q1 Load Transient Waveform for Legacy Chip
GUID-7C5464F5-3CFE-4A6F-905D-5A1FE1FFDF7C-low.svgFigure 8-9 TPS71533-Q1 Fast Line Transient Waveform for New Chip
GUID-96DBF883-59F3-4C30-9A18-EE0299DD7951-low.svgFigure 8-6 TPS71533-Q1 Power-Up and Power-Down Waveform for New Chip
GUID-7C092A47-6F6F-4A9C-A124-33610EC1EAB0-low.svgFigure 8-8 TPS71533-Q1 Load Transient Waveform for New Chip
GUID-F9B77C4B-1ACB-4D39-B13D-9A18B87ECB16-low.svgFigure 8-10 TPS71533-Q1 Dropout Exit Transient Response for New Chip