ZHCSDC1D September   2013  – October 2018 TAS5766M , TAS5768M

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      智能放大器概览
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
    7. 6.7 Electrical Characteristics
    8. 6.8 Timing Requirements - I2C Bus Timing
    9. 6.9 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart SOA
      2. 7.3.2 Smart BASS
      3. 7.3.3 Smart Protection
      4. 7.3.4 Implementing a Real World Design
      5. 7.3.5 Modulation Schemes
        1. 7.3.5.1 BD-Modulation
        2. 7.3.5.2 1SPW-Modulation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Protection System
        1. 7.4.1.1 Over Current Protection
        2. 7.4.1.2 Thermal Protection
        3. 7.4.1.3 DC Protection
      2. 7.4.2 Reset and System Clock Functions
        1. 7.4.2.1 Power-On Reset Function
        2. 7.4.2.2 System Clock Input
      3. 7.4.3 System Clock PLL Mode
      4. 7.4.4 Clock Generation and PLL
      5. 7.4.5 PLL Calculation
      6. 7.4.6 Audio Data Interface
        1. 7.4.6.1 Audio Serial Interface
        2. 7.4.6.2 PCM Audio Data Formats and Timing
      7. 7.4.7 TAS576xM Audio Processing Options
        1. 7.4.7.1  Overview
        2. 7.4.7.2  miniDSP Instruction Register
        3. 7.4.7.3  Digital Output
        4. 7.4.7.4  Software
        5. 7.4.7.5  Process Flow
        6. 7.4.7.6  Zero Data Detect
        7. 7.4.7.7  Power Save Modes
        8. 7.4.7.8  XSMT Pin (Soft Mute/Soft Un-Mute)
        9. 7.4.7.9  External Power Sense Undervoltage Protection Mode
        10. 7.4.7.10 Recommended Power Down Sequence
          1. 7.4.7.10.1 XSMT = 0
          2. 7.4.7.10.2 Clock Error Detect
          3. 7.4.7.10.3 Planned Shutdown
    5. 7.5 Programming
      1. 7.5.1 I2C Interface and Slave Address
      2. 7.5.2 Slave Address
      3. 7.5.3 Register Address Auto-Increment Mode
      4. 7.5.4 Packet Protocol
        1. Table 18. Read / Write Operation – Basic I2C Framework
      5. 7.5.5 Write Register
        1. Table 19. Write Operation
        2. 7.5.5.1   Read Register
          1. Table 20. Read Operation
    6. 7.6 Register Maps
  8. Applications and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Component Selection Criteria
      2. 8.1.2 Component Selection Impact on Board Layout, Component Placement, and Trace Routing
      3. 8.1.3 Amplifier Output Filtering
    2. 8.2 Typical Applications
      1. 8.2.1 Stereo Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Gain Setting and Output Switch Frequency
          2. 8.2.1.2.2 Gain Setting and Supply Voltage
          3. 8.2.1.2.3 DAC to AMP AC Coupling
          4. 8.2.1.2.4 Bootstrap Capacitors
        3. 8.2.1.3 BTL Application Curves
      2. 8.2.2 Mono/PBTL Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 PBTL Application Curves
      3. 8.2.3 QFN BTL Application Diagram
        1. 8.2.3.1 Design Requirements
  9. Power Supply Recommendations
    1. 9.1 AVDD, DVDD, CPVDD Supply
    2. 9.2 GVDD Supply
    3. 9.3 PVCC, AVCC Power Supply
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Register Map Information
    1. 11.1 Detailed Register Map Descriptions
      1. 11.1.1 Register Map Summary
      2. 11.1.2 Page 0 Registers
        1. 11.1.2.1  Page 0 / Register 1 (Hex 0x01)
        2. 11.1.2.2  Page 0 / Register 2 (Hex 0x02)
        3. 11.1.2.3  Page 0 / Register 3 (Hex 0x03)
        4. 11.1.2.4  Page 0 / Register 4 (Hex 0x04)
        5. 11.1.2.5  Page 0 / Register 7 (Hex 0x07)
        6. 11.1.2.6  Page 0 / Register 8 (Hex 0x08)
        7. 11.1.2.7  Page 0 / Register 9 (Hex 0x09)
        8. 11.1.2.8  Page 0 / Register 10 (Hex 0x0A)
        9. 11.1.2.9  Page 0 / Register 12 (Hex 0x0C)
        10. 11.1.2.10 Page 0 / Register 13 (Hex 0x0D)
        11. 11.1.2.11 Page 0 / Register 20 (Hex 0x14)
        12. 11.1.2.12 Page 0 / Register 21 (Hex 0x15)
        13. 11.1.2.13 Page 0 / Register 22 (Hex 0x16)
        14. 11.1.2.14 Page 0 / Register 23 (Hex 0x17)
        15. 11.1.2.15 Page 0 / Register 24 (Hex 0x18)
        16. 11.1.2.16 Page 0 / Register 27 (Hex 0x1B)
        17. 11.1.2.17 Page 0 / Register 28 (Hex 0x1C)
        18. 11.1.2.18 Page 0 / Register 29 (Hex 0x1D)
        19. 11.1.2.19 Page 0 / Register 30 (Hex 0x1E)
        20. 11.1.2.20 Page 0 / Register 32 (Hex 0x20)
        21. 11.1.2.21 Page 0 / Register 33 (Hex 0x21)
        22. 11.1.2.22 Page 0 / Register 34 (Hex 0x22)
        23. 11.1.2.23 Page 0 / Register 35 (Hex 0x23)
        24. 11.1.2.24 Page 0 / Register 36 (Hex 0x24)
        25. 11.1.2.25 Page 0 / Register 37 (Hex 0x25)
        26. 11.1.2.26 Page 0 / Register 40 (Hex 0x28)
        27. 11.1.2.27 Page 0 / Register 41 (Hex 0x29)
        28. 11.1.2.28 Page 0 / Register 42 (Hex 0x2A)
        29. 11.1.2.29 Page 0 / Register 43 (Hex 0x2B)
        30. 11.1.2.30 Page 0 / Register 44 (Hex 0x2C)
        31. 11.1.2.31 Page 0 / Register 59 (Hex 0x3B)
        32. 11.1.2.32 Page 0 / Register 65 (Hex 0x41)
        33. 11.1.2.33 Page 0 / Register 66 (Hex 0x42)
        34. 11.1.2.34 Page 0 / Register 82 (Hex 0x52)
        35. 11.1.2.35 Page 0 / Register 83 (Hex 0x53)
        36. 11.1.2.36 Page 0 / Register 84 (Hex 0x54)
        37. 11.1.2.37 Page 0 / Register 85 (Hex 0x55)
        38. 11.1.2.38 Page 0 / Register 86 (Hex 0x56)
        39. 11.1.2.39 Page 0 / Register 87 (Hex 0x57)
        40. 11.1.2.40 Page 0 / Register 90 (Hex 0x5A)
        41. 11.1.2.41 Page 0 / Register 91 (Hex 0x5B)
        42. 11.1.2.42 Page 0 / Register 92 (Hex 0x5C)
        43. 11.1.2.43 Page 0 / Register 93 (Hex 0x5D)
        44. 11.1.2.44 Page 0 / Register 94 (Hex 0x5E)
        45. 11.1.2.45 Page 0 / Register 95 (Hex 0x5F)
        46. 11.1.2.46 Page 0 / Register 108 (Hex 0x6C)
        47. 11.1.2.47 Page 0 / Register 118 (Hex 0x76)
        48. 11.1.2.48 Page 0 / Register 119 (Hex 0x77)
        49. 11.1.2.49 Page 0 / Register 120 (Hex 0x78)
        50. 11.1.2.50 Page 0 / Register 121 (Hex 0x79)
      3. 11.1.3 Page 1 Registers
        1. 11.1.3.1 Page 1 / Register 2 (Hex 0x02)
        2. 11.1.3.2 Page 1 / Register 5 (Hex 0x05)
        3. 11.1.3.3 Page 1 / Register 6 (Hex 0x06)
        4. 11.1.3.4 Page 1 / Register 7 (Hex 0x07)
        5. 11.1.3.5 Page 1 / Register 8 (Hex 0x08)
      4. 11.1.4 Page 44 Registers
        1. 11.1.4.1 Page 44 / Register 1 (Hex 0x01)
  12. 12器件和文档支持
    1. 12.1 相关链接
    2. 12.2 商标
    3. 12.3 静电放电警告
    4. 12.4 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

PLL Calculation

The TAS576xM has an on-chip PLL with fractional multiplication to generate the clock frequency needed by the audio DAC, Negative Charge Pump, Modulator and Digital Signal Processing blocks. The programmability of the PLL allows operation from a wide variety of clocks that may be available in the system. The PLL input (PLLCKIN) supports clock frequencies from 512 kHz to 50 MHz and is register programmable to enable generation of required sampling rates with fine precision.

The PLL is enabled by default. The PLL can be turned on by writing to Page 0, Register 4, D(0). When the PLL is enabled, the PLL output clock PLLCK is given by Equation 1:

Equation 1. TAS5766M TAS5768M Eq1_PLLCK_las965.gif

R = 1, 2, 3,4, … 15, 16
J = 0 4,5,6, … 63 and D = 0000, 0001, 0002, … 9999
K = [J value].[D value]
P 0 1, 2, 3, … 15
R, J, D and P are programmable. J is the integer portion of K (the number to the left of the decimal point) while D is the fraction portion of K (the number to the right of the decimal point, assuming four digits of precision).

Examples:

  • If K = 8.5, then J = 8, D = 5000
  • If K = 7.12, then J = 7, D = 1200
  • If K = 14.03, then J = 14, D = 0300
  • If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000, the following conditions must be satisfied:

  • 1 MHz ≤ ( PLLCKIN / P ) ≤20 MHz
  • 64 MHz ≤ (PLLCKIN x K x R / P ) ≤ 100 MHz
  • 1 ≤ J ≤ 63

When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied:

  • 6.667 MHz ≤ PLLCLKIN / P ≤ 20 MHz
  • 64 MHz ≤ (PLLCKIN x K x R / P ) ≤ 100 MHz
  • 4 ≤ J ≤ 11
  • R = 1

When the PLL is enabled:

  • fS = (PLLCLKIN × K × R) / (2048 × P)
  • The value of N is selected so that fS × N = PLLCLKIN x K x R / P is in the allowable range.

Example: MCLK = 12 MHz and fS = 44.1 kHz, (N=2048)
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264

Example: MCLK = 12 MHz and fS = 48.0 kHz, (N=2048)
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

Values are written to the registers in Table 6.

Table 6. PLL Registers

DIVIDER FUNCTION BITS
PLLE PLL enable Page 0, Register 4, D(0)
PPDV PLL P Page 0, Register 20, D(3:0)
PJDV PLL J Page 0, Register 21, D(5:0)
PDDV PLL D Page 0, Register 22, D(5:0)
Page 0, Register 23, D(7:0)
PRDV PLL R Page 0, Register 24, D(3:0)

Table 7. PLL Configuration Recommendations

COLUMN DESCRIPTION
fS (kHz) Sampling frequency
RSCLK Ration between sampling frequency and SCLK frequency (SCLK frequency = RSCLK x sampling frequency)
SCLK (MHz) System master clock frequency at SCLK input (pin 22)
PLL VCO (MHz) PLL VCO frequency as PLLCK
P One of the PLL coefficients
PLL REF (MHz) Internal reference clock frequency which is produced by SCLK / P
M = K × R The final PLL multiplication factor computed from K and R as described in Equation 1
K = J.D One of the PLL coefficients
R One of the PLL coefficients
PLL fS Ratio between fS and PLL VCO frequency (PLL VCO / fS)
DSP fS Ratio between operating clock rate and fS (PLL fS / NMAC)
NMAC The clock divider value in Table 4
DSP CLK (MHz) The operating frequency as DSPCK in Clock Generation and PLL
MOD fS Ratio between DAC operating clock frequency and fS (PLL fS / NDAC)
MOD f(kHz) DAC operating frequency as DACCK in Clock Generation and PLL
NDAC DAC clock divider value in Table 4
DOSR OSR clock divider value in Table DOSR 7 for generating OSRCK in Clock Generation and PLL. DOSR must be chosen so that MOD fS / DOSR = 16 for correct operation.
NCP NCP (negative charge pump) clock divider value in Table 4
CP f Negative charge pump clock frequency (fS × MOD fS / NCP)
% Error Percentage of error between PLL VCO / PLL fS and fS (mismatch error).
This number is typically zero but can be non-zero especially when K is not an integer (D is % Error not zero).
This number may be non-zero only when the TAS576xM acts as a master

Table 8. Recommended Clock Divider Settings for PLL as Master Clock

44.1 kHz
RSCLK 32 64 128 192 256 384 512 768 1024
SCLK (MHz) 1.4112 2.8224 5.6448 8.4672 11.2896 16.9344 22.5792 33.8688 45.1584
PLL VCO (MHz) 90.3168 90.3168 90.3168 90.3168 90.3168 90.3168 90.3168 90.3168 90.3168
P 1 1 1 3 2 3 3 3 3
PLL REF (MHz) 1.4112 2.8224 5.6448 2.8224 5.6448 5.6448 7.526 11.29 15.053
M = K×R 64 32 16 32 16 16 12 8 6
K = J.D 32 16 16 32 16 16 12 8 6
R 2 2 1 1 1 1 1 1 1
PLL fS 2048 2048 2048 2048 2048 2048 2048 2048 2048
DSP fS 1024 1024 1024 1024 1024 1024 1024 1024 1024
NMAC 2 2 2 2 2 2 2 2 2
DSP CLK (MHz) 45.1584 45.1584 45.1584 45.1584 45.1584 45.1584 45.1584 45.1584 45.1584
MOD fS 128 128 128 128 128 128 128 128 128
MOD f (kHz) 5644.8 5644.8 5644.8 5644.8 5644.8 5644.8 5644.8 5644.8 5644.8
NDAC 16 16 16 16 16 16 16 16 16
DOSR 8 8 8 8 8 8 8 8 8
% ERROR 0 0 0 0 0 0 0 0 0
NCP 4 4 4 4 4 4 4 4 4
CP f (kHz) 1411.2 1411.2 1411.2 1411.2 1411.2 1411.2 1411.2 1411.2 1411.2
48kHz
RSCLK 32 64 128 192 256 384 512 768 1024
SCLK (MHz) 1.536 3.072 6.144 9.216 12.288 18.432 24.576 36.864 49.152
PLL VCO (MHz) 98.304 98.304 98.304 98.304 98.304 98.304 98.304 98.304 98.304
P 1 1 1 3 2 3 3 3 3
PLL REF (MHz) 1.536 3.072 6.144 3.072 6.144 6.144 8.192 12.288 16.384
M = K×R 64 32 16 32 16 16 12 8 6
K = J.D 32 16 16 32 16 16 12 8 6
R 2 2 1 1 1 1 1 1 1
PLL fS 2048 2048 2048 2048 2048 2048 2048 2048 2048
DSP fS 1024 1024 1024 1024 1024 1024 1024 1024 1024
NMAC 2 2 2 2 2 2 2 2 2
DSP CLK (MHz) 49.152 49.152 49.152 49.152 49.152 49.152 49.152 49.152 49.152
MOD fS 128 128 128 128 128 128 128 128 128
MOD f (kHz) 6144 6144 6144 6144 6144 6144 6144 6144 6144
NDAC 16 16 16 16 16 16 16 16 16
DOSR 8 8 8 8 8 8 8 8 8
% ERROR 0 0 0 0 0 0 0 0 0
NCP 4 4 4 4 4 4 4 4 4
CP f (kHz) 1536 1536 1536 1536 1536 1536 1536 1536 1536