ZHCSDC1D September 2013 – October 2018 TAS5766M , TAS5768M
PRODUCTION DATA.
Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
---|---|---|---|---|---|---|---|---|---|
32 | 0x20 | RSV | DBCK6 | DBCK5 | DBCK4 | DBCK3 | DBCK2 | DBCK1 | DBCK0 |
Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
RSV | Reserved | ||||||||
Reserved. Do not access. | |||||||||
DBCK[6:0] | Master Mode BCK Divider | ||||||||
These bits set the SCK divider value to generate I2S master BCK clock. | |||||||||
Default value: 0000000 | |||||||||
0000000: Divide by 1 | |||||||||
0000001: Divide by 2 | |||||||||
... | |||||||||
1111111: Divide by 128 |