ZHCSDC1D September 2013 – October 2018 TAS5766M , TAS5768M
PRODUCTION DATA.
Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
---|---|---|---|---|---|---|---|---|---|
27 | 0x1B | RSV | DDSP6 | DDSP5 | DDSP4 | DDSP3 | DDSP2 | DDSP1 | DDSP0 |
Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
RSV | Reserved | ||||||||
Reserved. Do not access. | |||||||||
DDSP[6:0] | DSP Clock Divider | ||||||||
These bits set the source clock divider value for the DSP clock. These bits are ignored in clock auto set mode. | |||||||||
Default value: 0000000 | |||||||||
0000000: Divide by 1 | |||||||||
0000001: Divide by 2 | |||||||||
... | |||||||||
1111111: Divide by 128 |