ZHCSDC1D September 2013 – October 2018 TAS5766M , TAS5768M
PRODUCTION DATA.
Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
---|---|---|---|---|---|---|---|---|---|
36 | 0x24 | IDAC_LSB7 | IDAC_LSB6 | IDAC_LSB5 | IDAC_LSB4 | IDAC_LSB3 | IDAC_LSB2 | IDAC_LSB1 | IDAC_LSB0 |
Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
IDAC_LSB[7:0] | IDAC (LSB) | ||||||||
Least-significant 8 bits to specify the number of DSP clock cycles available in one audio frame. | |||||||||
Default value: 00000000 | |||||||||