ZHCS065G March 2011 – January 2024 DAC3482
PRODUCTION DATA
Register Name | Address | Bit | Name | Function | Default Value |
---|---|---|---|---|---|
config25 | 0x19 | 15:8 | pll_m(7:0) | M portion of the M/N divider of the PLL. If pll_m<7> = 0, the M divider value has the range of pll_m<6:0>, spanning from 4 to 127. (0, 1, 2, and 3 are not valid.) If pll_m<7> = 1, the M divider value has the range of 2 × pll_m<6:0>, spanning from 8 to 254. (0, 2, 4, and 6 are not valid. M divider has even values only.) | 00000100 |
7:4 | pll_n(3:0) | N portion of the M/N divider of the PLL. 0000: 1 0001: 2 0010: 3 0011: 4 0100: 5 0101: 6 0110: 7 0111: 8 1000: 9 1001: 10 1010: 11 1011: 12 1100: 13 1101: 14 1110: 15 1111: 16 | 0100 | ||
3:2 | pll_vcoitune(1:0) | PLL VCO bias tuning bits. Set to 01b for normal PLL operation. | 00 | ||
1:0 | Reserved | Reserved for factory use. | 00 |