ZHCSGU6A september   2017  – july 2023 ADS8588H

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: CONVST Control
    7. 6.7  Timing Requirements: Data Read Operation
    8. 6.8  Timing Requirements: Parallel Data Read Operation, CS and RD Tied Together
    9. 6.9  Timing Requirements: Parallel Data Read Operation, CS and RD Separate
    10. 6.10 Timing Requirements: Serial Data Read Operation
    11. 6.11 Timing Requirements: Byte Mode Data Read Operation
    12. 6.12 Timing Requirements: Oversampling Mode
    13. 6.13 Timing Requirements: Exit Standby Mode
    14. 6.14 Timing Requirements: Exit Shutdown Mode
    15. 6.15 Switching Characteristics: CONVST Control
    16. 6.16 Switching Characteristics: Parallel Data Read Operation, CS and RD Tied Together
    17. 6.17 Switching Characteristics: Parallel Data Read Operation, CS and RD Separate
    18. 6.18 Switching Characteristics: Serial Data Read Operation
    19. 6.19 Switching Characteristics: Byte Mode Data Read Operation
    20. 6.20 Timing Diagrams
    21. 6.21 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Analog Input Impedance
      3. 7.3.3  Input Clamp Protection Circuit
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  Third-Order, Low-Pass Filter (LPF)
      6. 7.3.6  ADC Driver
      7. 7.3.7  Digital Filter and Noise
      8. 7.3.8  Reference
        1. 7.3.8.1 Internal Reference
        2. 7.3.8.2 External Reference
        3. 7.3.8.3 Supplying One VREF to Multiple Devices
      9. 7.3.9  ADC Transfer Function
      10. 7.3.10 ADS8588H Device Family Comparison
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Interface: Pin Description
        1. 7.4.1.1  REFSEL (Input)
        2. 7.4.1.2  RANGE (Input)
        3. 7.4.1.3  STBY (Input)
        4. 7.4.1.4  PAR/SER/BYTE SEL (Input)
        5. 7.4.1.5  CONVSTA, CONVSTB (Input)
        6. 7.4.1.6  RESET (Input)
        7. 7.4.1.7  RD/SCLK (Input)
        8. 7.4.1.8  CS (Input)
        9. 7.4.1.9  OS[2:0]
        10. 7.4.1.10 BUSY (Output)
        11. 7.4.1.11 FRSTDATA (Output)
        12. 7.4.1.12 DB15/BYTE SEL
        13. 7.4.1.13 DB14/HBEN
        14. 7.4.1.14 DB[13:9]
        15. 7.4.1.15 DB8/DOUTB
        16. 7.4.1.16 DB7/DOUTA
        17. 7.4.1.17 DB[6:0]
      2. 7.4.2 Device Modes of Operation
        1. 7.4.2.1 Power-Down Modes
          1. 7.4.2.1.1 Standby Mode
          2. 7.4.2.1.2 Shutdown Mode
        2. 7.4.2.2 Conversion Control
          1. 7.4.2.2.1 Simultaneous Sampling on All Input Channels
          2. 7.4.2.2.2 Simultaneous Sampling Two Sets of Input Channels
        3. 7.4.2.3 Data Read Operation
          1. 7.4.2.3.1 Parallel Data Read
          2. 7.4.2.3.2 Parallel Byte Data Read
          3. 7.4.2.3.3 Serial Data Read
          4. 7.4.2.3.4 Data Read During Conversion
        4. 7.4.2.4 Oversampling Mode of Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

GUID-3344832D-098B-48E5-A4C7-FE5AB7937019-low.svgFigure 5-1 PM Package,64-Pin LQFP(Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
AGND 2, 26, 35, 40, 41, 47 P Analog ground pins
AIN_1GND 50 AI Analog input channel 1: negative input.
AIN_1P 49 AI Analog input channel 1: positive input.
AIN_2GND 52 AI Analog input channel 2: negative input.
AIN_2P 51 AI Analog input channel 2: positive input.
AIN_3GND 54 AI Analog input channel 3: negative input.
AIN_3P 53 AI Analog input channel 3: positive input.
AIN_4GND 56 AI Analog input channel 4: negative input.
AIN_4P 55 AI Analog input channel 4: positive input.
AIN_5GND 58 AI Analog input channel 5: negative input.
AIN_5P 57 AI Analog input channel 5: positive input.
AIN_6GND 60 AI Analog input channel 6: negative input.
AIN_6P 59 AI Analog input channel 6: positive input.
AIN_7GND 62 AI Analog input channel 7: negative input.
AIN_7P 61 AI Analog input channel 7: positive input.
AIN_8GND 64 AI Analog input channel 8: negative input.
AIN_8P 63 AI Analog input channel 8: positive input.
AVDD 1, 37, 38, 48 P Analog supply pins. Decouple these pins to the closest AGND pins
(see the Power Supply Recommendations section).
BUSY 14 DO Active high digital output indicating ongoing conversion
(see the BUSY (Output) section).
CONVSTA 9 DI Active high logic input to control start of conversion for first half count of device input channels (see the CONVSTA, CONVSTB (Input) section).
CONVSTB 10 DI Active high logic input to control start of conversion for second half count of device input channels (see the CONVSTA, CONVSTB (Input) section).
CS 13 DI Active low logic input chip-select signal (see the CS (Input) section).
DB0 16 DO Data output DB0 (LSB) in parallel interface mode (see the DB[6:0] section).
DB1 17 DO Data output DB1 in parallel interface mode (see the DB[6:0] section).
DB2 18 DO Data output DB2 in parallel interface mode (see the DB[6:0] section).
DB3 19 DO Data output DB3 in parallel interface mode (see the DB[6:0] section).
DB4 20 DO Data output DB4 in parallel interface mode (see the DB[6:0] section).
DB5 21 DO Data output DB5 in parallel interface mode (see the DB[6:0] section).
DB6 22 DO Data output DB6 in parallel interface mode (see the DB[6:0] section).
DB7/DOUTA 24 DO Multifunction logic output pin (see the DB7/DOUTA section):
this pin is data output DB7 in parallel and parallel byte interface mode;
this pin is a data output pin in serial interface mode.
DB8/DOUTB 25 DO Multifunction logic output pin (see the DB8/DOUTB section):
this pin is data output DB8 in parallel interface mode;
this pin is a data output pin in serial interface mode.
DB9 27 DO Data output DB9 in parallel interface mode (see the DB[13:9] section).
DB10 28 DO Data output DB10 in parallel interface mode (see the DB[13:9] section).
DB11 29 DO Data output DB11 in parallel interface mode (see the DB[13:9] section).
DB12 30 DO Data output DB12 in parallel interface mode (see the DB[13:9] section).
DB13 31 DO Data output DB13 in parallel interface mode (see the DB[13:9] section).
DB14 32 DO Multifunction logic input or output pin (see the DB14/HBEN section):
this pin is data output DB14 in parallel interface mode;
this pin is a control input pin for byte selection (high or low) in parallel byte interface mode.
DB15 33 DO Multifunction logic input or output pin (see the DB14/HBEN section):
this pin is data output DB14 in parallel interface mode;
this pin is a control input pin for byte selection (high or low) in parallel byte interface mode.
DVDD 23 P Digital supply pin; decouple with AGND on pin 26.
FRSTDATA 15 DO Active high digital output indicating data read back from channel 1 of the devices (see the FRSTDATA (Output) section).
OS0 3 DI Oversampling mode control pin
(see the Oversampling Mode of Operation section).
OS1 4 DI Oversampling mode control pin
(see the Oversampling Mode of Operation section).
OS2 5 DI Oversampling mode control pin
(see the Oversampling Mode of Operation section).
PAR/SER/BYTE SEL 6 DI Logic input pin to select between parallel or serial or parallel byte interface mode (see the Data Read Operation section).
RANGE 8 DI Multifunction logic input pin (see the RANGE (Input) section):
when the STBY pin is high, this pin selects the input range of the device (±10 V or ±5 V); when the STBY pin is low, this pin selects between the standby and shutdown modes.
RD/SCLK 12 DI Multifunction logic input pin (see the RD/SCLK (Input) section):
this pin is an active-low ready input pin in parallel and parallel byte interface;
this pin is a clock input pin in serial interface mode.
REFCAPA 44 AO Reference amplifier output pins. This pin must be shorted to REFCAPB and decoupled to AGND using a low ESR, 22-µF ceramic capacitor.
REFCAPB 45 AO Reference amplifier output pins. This pin must be shorted to REFCAPA and decoupled to AGND using a low ESR, 22-µF ceramic capacitor.
REFGND 43, 46 P Reference GND pin. This pin must be shorted to the analog GND plane and decoupled with REFIN/REFOUT on pin 42 using a 10-µF capacitor.
REFIN/REFOUT 42 AIO This pin acts as an internal reference output when REFSEL is high;
this pin functions as an input pin for the external reference when REFSEL is low;
decouple with REFGND on pin 43 using a 10-µF capacitor.
REFSEL 34 DI Active high logic input to enable the internal reference
(see the REFSEL (Input) section).
REGCAP1 36 AO Output pin 1 for the internal voltage regulator; decouple separately to AGND using a 1-µF capacitor.
REGCAP2 39 AO Output pin 2 for the internal voltage regulator; decouple separately to AGND using a 1-µF capacitor.
RESET 11 DI Active high logic input to reset the device digital logic
(see the REFSEL (Input) section).
STBY 7 DI Active low logic input to enter the device into one of the two power-down modes: standby or shutdown (see the Power-Down Modes section).
(1) AI = analog input; AO = analog output; AIO = analog input/output; DI = digital input; DO = digital output; DIO = digital input/output; P = power supply; and NC = no connect.