The ADS8588H also supports a serial interface mode for reading the device output data. This interface mode is selected by applying a logic high input on the PAR/SER/BYTE SEL input pin and a logic low input on the DB15/BYTE SEL input pin. This interface mode uses a CS control input, a communication clock input (SCLK), BUSY and FRSTDATA output indicators, and serial data output lines DOUTA and DOUTB.

Figure 6-5 illustrates the timing diagram for data read in serial mode for one channel of the ADC, framed by the CS signal. When the CS input is high, the serial data output and FRSTDATA output lines are in tri-state and the SCLK input is ignored. On the falling edge of the CS signal, the output lines become active and the MSB of the conversion result comes out on DOUTA, DOUTB. The MSB can be read by the host processor on the next falling edge of the SCLK signal. The remaining 15 bits of the conversion result are output on the subsequent rising edges of the SCLK signal and can be read by the host processor on the corresponding falling edges. Thus, a total of 16 SCLK cycles are required to clock out 16 bits of conversion result for each channel and the same process can be repeated for the remaining channels in an ascending order. The CS input can be left at a logic low level for the entire data retrieval process for all analog channels or used to frame the retrieval of the 16-bit output data for each analog channel.

The ADS8588H can output the conversion on one or both of the serial data output lines, DOUTA and DOUTB. The conversion results from the first set of channels (channels 1-4) appear first on DOUTA, followed by the second set of channels (channels 5-8) if only DOUTA is used for reading data. This order is reversed for DOUTB, in which the second set of channels appear first followed by the first set of channels. The use of both data output lines reduces the time needed for data retrieval and a higher throughput can therefore be achieved in this mode.

The FRSTDATA output is in tri-state when the CS signal is high. As illustrated in Figure 6-5, FRSTDATA goes high on the first falling edge of the CS signal when the MSB of channel 1 is output on DOUTA. The FRSTDATA output remains high for the next 16 SCLK cycles until all data bits of channel 1 are read from the device. The FRSTDATA output returns to a logic low level at the 16th falling edge of the SCLK signal. If data are also read on DOUTB in serial mode, then FRSTDATA remains high when the first channel of the second set of channels is read from the device. The high state of FRSTDATA corresponds to channel 5.

Based on the above description of the different pins in the serial interface mode, conversion data can be read out of the device in several different ways. Some example recommendations are provided below:

• The conversion data can be read out of the device using only one of the two serial output lines, DOUTA or DOUTB. In this case, using DOUTA for output data read back is recommended because channel 1 data appear first on DOUTA followed by the data for other channels in ascending order. To read the data for all channels, provide a total of 16 × 8 = 128 SCLK cycles. This entire data frame can be created within a single CS pulse or each group of 16 SCLK cycles can be individually framed by the CS signal. The primary disadvantage of using just one data line for reading conversion data is that the throughput is reduced if a data read operation is performed after conversion. Figure 7-18 illustrates this operation.
• Alternatively, only DOUTB can be used for reading the conversion data from all channels. In this case, everything else remains the same and the output bit stream contains data for all channels in the following order: channels 5, 6, 7, 8, 1, 2, 3, and 4. Figure 7-18 illustrates this operation.
  Figure 7-18 Data Read Back in the Serial Interface Using Either DOUTA or DOUTB Timing Diagram
• In order to minimize the time for the data read operation in serial mode, both DOUTA and DOUTB can be used to read data out of the device. In this case, the conversion results from the first set of channels (channels 1-4) appear on DOUTA and the conversion results from the second set of channels (channels 5-8) appear first on DOUTB. To read the data for all channels, provide a total of 16 × 4 = 64 SCLK cycles. This entire data frame can be created within a single CS pulse or each group of 16 SCLK cycles can be individually framed by the CS signal. Figure 7-19 shows an example timing diagram.
  Figure 7-19 Data Read Back in the Serial Interface Using Both DOUTA and DOUTB Timing Diagram