ZHCSGU6A september   2017  – july 2023 ADS8588H

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: CONVST Control
    7. 6.7  Timing Requirements: Data Read Operation
    8. 6.8  Timing Requirements: Parallel Data Read Operation, CS and RD Tied Together
    9. 6.9  Timing Requirements: Parallel Data Read Operation, CS and RD Separate
    10. 6.10 Timing Requirements: Serial Data Read Operation
    11. 6.11 Timing Requirements: Byte Mode Data Read Operation
    12. 6.12 Timing Requirements: Oversampling Mode
    13. 6.13 Timing Requirements: Exit Standby Mode
    14. 6.14 Timing Requirements: Exit Shutdown Mode
    15. 6.15 Switching Characteristics: CONVST Control
    16. 6.16 Switching Characteristics: Parallel Data Read Operation, CS and RD Tied Together
    17. 6.17 Switching Characteristics: Parallel Data Read Operation, CS and RD Separate
    18. 6.18 Switching Characteristics: Serial Data Read Operation
    19. 6.19 Switching Characteristics: Byte Mode Data Read Operation
    20. 6.20 Timing Diagrams
    21. 6.21 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Analog Input Impedance
      3. 7.3.3  Input Clamp Protection Circuit
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  Third-Order, Low-Pass Filter (LPF)
      6. 7.3.6  ADC Driver
      7. 7.3.7  Digital Filter and Noise
      8. 7.3.8  Reference
        1. 7.3.8.1 Internal Reference
        2. 7.3.8.2 External Reference
        3. 7.3.8.3 Supplying One VREF to Multiple Devices
      9. 7.3.9  ADC Transfer Function
      10. 7.3.10 ADS8588H Device Family Comparison
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Interface: Pin Description
        1. 7.4.1.1  REFSEL (Input)
        2. 7.4.1.2  RANGE (Input)
        3. 7.4.1.3  STBY (Input)
        4. 7.4.1.4  PAR/SER/BYTE SEL (Input)
        5. 7.4.1.5  CONVSTA, CONVSTB (Input)
        6. 7.4.1.6  RESET (Input)
        7. 7.4.1.7  RD/SCLK (Input)
        8. 7.4.1.8  CS (Input)
        9. 7.4.1.9  OS[2:0]
        10. 7.4.1.10 BUSY (Output)
        11. 7.4.1.11 FRSTDATA (Output)
        12. 7.4.1.12 DB15/BYTE SEL
        13. 7.4.1.13 DB14/HBEN
        14. 7.4.1.14 DB[13:9]
        15. 7.4.1.15 DB8/DOUTB
        16. 7.4.1.16 DB7/DOUTA
        17. 7.4.1.17 DB[6:0]
      2. 7.4.2 Device Modes of Operation
        1. 7.4.2.1 Power-Down Modes
          1. 7.4.2.1.1 Standby Mode
          2. 7.4.2.1.2 Shutdown Mode
        2. 7.4.2.2 Conversion Control
          1. 7.4.2.2.1 Simultaneous Sampling on All Input Channels
          2. 7.4.2.2.2 Simultaneous Sampling Two Sets of Input Channels
        3. 7.4.2.3 Data Read Operation
          1. 7.4.2.3.1 Parallel Data Read
          2. 7.4.2.3.2 Parallel Byte Data Read
          3. 7.4.2.3.3 Serial Data Read
          4. 7.4.2.3.4 Data Read During Conversion
        4. 7.4.2.4 Oversampling Mode of Operation
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Mechanical, Packaging, and Orderable Information

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订购信息
Simultaneous Sampling on All Input Channels

The ADS8588H allows all analog input channels to be simultaneously sampled. In order to do so, the CONVSTA and CONVSTB signals must be tied together as shown in Figure 7-16 and a single CONVST signal must be used to control the sampling of all analog input channels of the device. Figure 7-16 also shows the sequence of events described in this section.

GUID-81D74A2C-5FEA-4507-9430-A6AE3809007C-low.gifFigure 7-16 Simultaneous Sampling of All Input Channels in Parallel Interface Timing Diagram

There are four events that describe the internal operation of the device when all input channels are simultaneously sampled and the data are read back. These events are:

  • Event 1: Simultaneous sampling of all analog input channels is initiated with the rising edge of the CONVST signal. The input signals on all channels are sampled at this same instant because both the CONVSTA and CONVSTB inputs are tied together. The sampled signals are then converted by the ADCs using a precise on-chip oscillator clock. At the beginning of the conversion phase of the ADC, the BUSY output goes high and remains high through a maximum-specified conversion time of tCONV (see the Timing Requirements: CONVST ControlTiming Requirements: CONVST Control table).
  • Event 2: At this instant, the ADC has completed the conversion for all input channels and the BUSY output goes to logic low. The falling edge of the BUSY signal indicates end of conversion and that the internal registers are updated with the conversion data. At this instant, the device is ready to output the correct conversion results for all channels on the parallel output bus (DB[15:0]), serial output lines (DOUTA, DOUTB), or parallel byte bus (DB[7:0]).
  • Event 3: This example shows the data read operation in parallel interface mode with both CS and RD tied together. After BUSY goes low, the first falling edges of CS and RD output the conversion result of channel 1 (AIN_1) on the parallel output bus. Similarly, the conversion results for the remaining channels are output on the parallel bus on subsequent falling edges of the CS and RD signals in a sequential manner. If all channels are not used in the conversion process, tie the unused channels to AGND or any known voltage within the selected input range. The ADC always converts all analog input channels and the results for unused channels are included in the output data stream, thus all unused channels must be tied to AGND or a known voltage within the range. The FRSTDATA output goes high on the first falling edges of the CS and RD signals, indicating that the parallel bus is carrying the output result from channel 1. On the next falling edge of the CS and RD signals, FRSTDATA goes low and stays low if the CS and RD inputs are low.
  • Event 4: After the conversion results for all analog channels are output from the device, the data frame can be terminated by pulling the CS and RD signals to logic high. The parallel bus and FRSTDATA output go to tri-state until the entire sequence is repeated beginning from event 1.

Events 1 and 2 are common to all interface modes of operation (parallel or serial or parallel byte).