AMIC110

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Sitara 处理器：Arm Cortex-A8、支持 10 余种以太网协议

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数据表

document-pdfAcrobat AMIC110 Sitara™ SoC 数据表 (Rev. D) (英语) PDF | HTML

AMIC110

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产品详情

CPU

1 Arm Cortex-A8

Frequency (MHz)

300

Protocols

EtherCAT, EtherNet/IP, Ethernet, Profibus, Profinet, Sercos

Hardware accelerators

Industrial communications subsystem, Programable real-time unit

Features

Networking

Rating

Catalog

Power supply solution

TPS650250, TPS65216

Operating temperature range (°C)

-40 to 105

CPU

1 Arm Cortex-A8

Frequency (MHz)

300

Protocols

EtherCAT, EtherNet/IP, Ethernet, Profibus, Profinet, Sercos

Hardware accelerators

Industrial communications subsystem, Programable real-time unit

Features

Networking

Rating

Catalog

Power supply solution

TPS650250, TPS65216

Operating temperature range (°C)

-40 to 105

NFBGA (ZCZ)

324

225 mm² (15 mm × 15 mm)

Up to 300-MHz Sitara™ ARM^® Cortex^®-A8 32‑Bit RISC Processor
- NEON™ SIMD Coprocessor
- 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)
- 256KB of L2 Cache With Error Correcting Code (ECC)
- 176KB of On-Chip Boot ROM
- 64KB of Dedicated RAM
- Emulation and Debug - JTAG
- Interrupt Controller (up to 128 Interrupt Requests)
On-Chip Memory (Shared L3 RAM)
- 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
- Accessible to All Masters
- Supports Retention for Fast Wakeup
External Memory Interfaces (EMIF)
- mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
  - mDDR: 200-MHz Clock (400-MHz Data Rate)
  - DDR2: 266-MHz Clock (532-MHz Data Rate)
  - DDR3: 400-MHz Clock (800-MHz Data Rate)
  - DDR3L: 400-MHz Clock (800-MHz Data Rate)
  - 16-Bit Data Bus
  - 1GB of Total Addressable Space
  - Supports One x16 or Two x8 Memory Device Configurations
- General-Purpose Memory Controller (GPMC)
  - Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
  - Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
  - Uses Hamming Code to Support 1-Bit ECC
- Error Locator Module (ELM)
  - Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
  - Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
- Supports Protocols such as EtherCAT^®, PROFIBUS, PROFINET, EtherNet/IP™, and More
- Two Programmable Real-Time Units (PRUs)
  - 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz
  - 8KB of Instruction RAM With Single-Error Detection (Parity)
  - 8KB of Data RAM With Single-Error Detection (Parity)
  - Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
  - Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal
- 12KB of Shared RAM With Single-Error Detection (Parity)
- Three 120-Byte Register Banks Accessible by Each PRU
- Interrupt Controller (INTC) for Handling System Input Events
- Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
- Peripherals Inside the PRU-ICSS:
  - One UART Port With Flow Control Pins, Supports up to 12 Mbps
  - One Enhanced Capture (eCAP) Module
  - Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
  - One MDIO Port
Power, Reset, and Clock Management (PRCM) Module
- Controls the Entry and Exit of Stand-By and Deep-Sleep Modes
- Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
- Clocks
  - Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
  - Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
  - Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I²C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock ⁽¹⁾)
- Power
  - Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])
  - Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX]⁽¹⁾, Peripherals and Infrastructure [PER])
  - Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])
  - Dynamic Voltage Frequency Scaling (DVFS)
Real-Time Clock (RTC)
- Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
- Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
- Independent Power-on-Reset (RTC_PWRONRSTn) Input
- Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
- Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)
- Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
Peripherals
- Up to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHY
- Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
  - Integrated Switch
  - Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces
  - Ethernet MACs and Switch Can Operate Independent of Other Functions
  - IEEE 1588v1 Precision Time Protocol (PTP)
- Up to Two Controller-Area Network (CAN) Ports
  - Supports CAN Version 2 Parts A and B
- Up to Two Multichannel Audio Serial Ports (McASPs)
  - Transmit and Receive Clocks up to 50 MHz
  - Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks
  - Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
  - Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
  - FIFO Buffers for Transmit and Receive (256 Bytes)
- Up to Six UARTs
  - All UARTs Support IrDA and CIR Modes
  - All UARTs Support RTS and CTS Flow Control
  - UART1 Supports Full Modem Control
- Up to Two Master and Slave McSPI Serial Interfaces
  - Up to Two Chip Selects
  - Up to 48 MHz
- Up to Three MMC, SD, SDIO Ports
  - 1-, 4- and 8-Bit MMC, SD, SDIO Modes
  - MMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V Operation
  - Up to 48-MHz Data Transfer Rate
  - Supports Card Detect and Write Protect
  - Complies With MMC4.3, SD, SDIO 2.0 Specifications
- Up to Three I²C Master and Slave Interfaces
  - Standard Mode (up to 100 kHz)
  - Fast Mode (up to 400 kHz)
- Up to Four Banks of General-Purpose I/O (GPIO) Pins
  - 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)
  - GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
- Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs
- Eight 32-Bit General-Purpose Timers
  - DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
  - DMTIMER4–DMTIMER7 are Pinned Out
- One Watchdog Timer
- 12-Bit Successive Approximation Register (SAR) ADC
  - 200K Samples per Second
  - Input can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
- Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs)
  - Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
  - Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
Device Identification
- Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
  - Production ID
  - Device Part Number (Unique JTAG ID)
  - Device Revision (Readable by Host ARM)
Debug Interface Support
- JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug
- Supports Device Boundary Scan
- Supports IEEE 1500
DMA
- On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
  - Transfers to and from On-Chip Memories
  - Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals)
Inter-Processor Communication (IPC)
- Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS
  - Mailbox Registers that Generate Interrupts
    - Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)
  - Spinlock has 128 Software-Assigned Lock Registers
Boot Modes
- Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
Package:
- 324-Pin S-PBGA-N324 Package
  (ZCZ Suffix), 0.80-mm Ball Pitch

⁽¹⁾The GFX [SGX530] and LCD modules are not supported for this family of devices, but the "LCD" and "GFX" names are still present in some PLL, power domain, or supply voltage names.

Up to 300-MHz Sitara™ ARM^® Cortex^®-A8 32‑Bit RISC Processor
- NEON™ SIMD Coprocessor
- 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)
- 256KB of L2 Cache With Error Correcting Code (ECC)
- 176KB of On-Chip Boot ROM
- 64KB of Dedicated RAM
- Emulation and Debug - JTAG
- Interrupt Controller (up to 128 Interrupt Requests)
On-Chip Memory (Shared L3 RAM)
- 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
- Accessible to All Masters
- Supports Retention for Fast Wakeup
External Memory Interfaces (EMIF)
- mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
  - mDDR: 200-MHz Clock (400-MHz Data Rate)
  - DDR2: 266-MHz Clock (532-MHz Data Rate)
  - DDR3: 400-MHz Clock (800-MHz Data Rate)
  - DDR3L: 400-MHz Clock (800-MHz Data Rate)
  - 16-Bit Data Bus
  - 1GB of Total Addressable Space
  - Supports One x16 or Two x8 Memory Device Configurations
- General-Purpose Memory Controller (GPMC)
  - Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
  - Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
  - Uses Hamming Code to Support 1-Bit ECC
- Error Locator Module (ELM)
  - Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
  - Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
- Supports Protocols such as EtherCAT^®, PROFIBUS, PROFINET, EtherNet/IP™, and More
- Two Programmable Real-Time Units (PRUs)
  - 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz
  - 8KB of Instruction RAM With Single-Error Detection (Parity)
  - 8KB of Data RAM With Single-Error Detection (Parity)
  - Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
  - Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal
- 12KB of Shared RAM With Single-Error Detection (Parity)
- Three 120-Byte Register Banks Accessible by Each PRU
- Interrupt Controller (INTC) for Handling System Input Events
- Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
- Peripherals Inside the PRU-ICSS:
  - One UART Port With Flow Control Pins, Supports up to 12 Mbps
  - One Enhanced Capture (eCAP) Module
  - Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
  - One MDIO Port
Power, Reset, and Clock Management (PRCM) Module
- Controls the Entry and Exit of Stand-By and Deep-Sleep Modes
- Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
- Clocks
  - Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
  - Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
  - Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I²C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock ⁽¹⁾)
- Power
  - Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])
  - Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX]⁽¹⁾, Peripherals and Infrastructure [PER])
  - Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])
  - Dynamic Voltage Frequency Scaling (DVFS)
Real-Time Clock (RTC)
- Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
- Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
- Independent Power-on-Reset (RTC_PWRONRSTn) Input
- Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
- Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)
- Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
Peripherals
- Up to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHY
- Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
  - Integrated Switch
  - Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces
  - Ethernet MACs and Switch Can Operate Independent of Other Functions
  - IEEE 1588v1 Precision Time Protocol (PTP)
- Up to Two Controller-Area Network (CAN) Ports
  - Supports CAN Version 2 Parts A and B
- Up to Two Multichannel Audio Serial Ports (McASPs)
  - Transmit and Receive Clocks up to 50 MHz
  - Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks
  - Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
  - Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
  - FIFO Buffers for Transmit and Receive (256 Bytes)
- Up to Six UARTs
  - All UARTs Support IrDA and CIR Modes
  - All UARTs Support RTS and CTS Flow Control
  - UART1 Supports Full Modem Control
- Up to Two Master and Slave McSPI Serial Interfaces
  - Up to Two Chip Selects
  - Up to 48 MHz
- Up to Three MMC, SD, SDIO Ports
  - 1-, 4- and 8-Bit MMC, SD, SDIO Modes
  - MMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V Operation
  - Up to 48-MHz Data Transfer Rate
  - Supports Card Detect and Write Protect
  - Complies With MMC4.3, SD, SDIO 2.0 Specifications
- Up to Three I²C Master and Slave Interfaces
  - Standard Mode (up to 100 kHz)
  - Fast Mode (up to 400 kHz)
- Up to Four Banks of General-Purpose I/O (GPIO) Pins
  - 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)
  - GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
- Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs
- Eight 32-Bit General-Purpose Timers
  - DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
  - DMTIMER4–DMTIMER7 are Pinned Out
- One Watchdog Timer
- 12-Bit Successive Approximation Register (SAR) ADC
  - 200K Samples per Second
  - Input can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
- Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs)
  - Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
  - Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
Device Identification
- Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
  - Production ID
  - Device Part Number (Unique JTAG ID)
  - Device Revision (Readable by Host ARM)
Debug Interface Support
- JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug
- Supports Device Boundary Scan
- Supports IEEE 1500
DMA
- On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
  - Transfers to and from On-Chip Memories
  - Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals)
Inter-Processor Communication (IPC)
- Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS
  - Mailbox Registers that Generate Interrupts
    - Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)
  - Spinlock has 128 Software-Assigned Lock Registers
Boot Modes
- Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
Package:
- 324-Pin S-PBGA-N324 Package
  (ZCZ Suffix), 0.80-mm Ball Pitch

⁽¹⁾The GFX [SGX530] and LCD modules are not supported for this family of devices, but the "LCD" and "GFX" names are still present in some PLL, power domain, or supply voltage names.

The AMIC110 device is a multiprotocol programmable industrial communications processor providing ready-to-use solutions for most industrial Ethernet and fieldbus communications slaves, as well as some masters. The device is based on the ARM Cortex-A8 processor, peripherals, and industrial interface options. The devices support high-level operating systems (HLOS). Processor SDK Linux^® and TI-RTOS are available free of charge from TI. Other RTOS are also offered by TI ecosystem partners. The AMIC110 microprocessor is an ideal companion communications chip to the C2000 family of microcontrollers for connected drives.

The AMIC110 microprocessor contains the subsystems shown in Figure 1-1 and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor. The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET IRT, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos III, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.

The AMIC110 device is a multiprotocol programmable industrial communications processor providing ready-to-use solutions for most industrial Ethernet and fieldbus communications slaves, as well as some masters. The device is based on the ARM Cortex-A8 processor, peripherals, and industrial interface options. The devices support high-level operating systems (HLOS). Processor SDK Linux^® and TI-RTOS are available free of charge from TI. Other RTOS are also offered by TI ecosystem partners. The AMIC110 microprocessor is an ideal companion communications chip to the C2000 family of microcontrollers for connected drives.

The AMIC110 microprocessor contains the subsystems shown in Figure 1-1 and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor. The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET IRT, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos III, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.

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AMIC120

正在供货

Sitara 处理器；Arm Cortex-A9、支持 10 余种以太网协议、编码器协议 AMIC120 includes protocols as AMIC 110 but is a higher performance Cortex - A9 processor with encoder protocols & cryptography

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顶层文档	类型	标题	格式选项	下载最新的英语版本		日期
*	数据表	AMIC110 Sitara™ SoC 数据表 (Rev. D)	PDF \| HTML			2019-12-12
*	勘误表	AMIC110 Sitara SoC Silicon Errata (Rev. 2.1)				2017-1-3
	白皮书	TI Sitara™ 处理器集成 PROFINET® 技术	PDF \| HTML			2026-4-17
	应用手册	TI 处理器和 MCU 上支持的工业通信协议 (Rev. F)	PDF \| HTML	英语版 (Rev.F)	PDF \| HTML	2025-9-22
	白皮书	深入了解工业以太网通信协议 (Rev. B)	PDF \| HTML	英语版 (Rev.B)		2021-6-3
	白皮书	Sitara™ 处理器上的 EtherCAT® (Rev. I)	PDF \| HTML	英语版 (Rev.I)		2021-6-3
	技术文章	How to affordably add EtherNet/IP, EtherCAT and PROFINET to an autonomous factory	PDF \| HTML			2020-8-24
	白皮书	EtherNet/IP on TI's Sitara AM335x Processors (Rev. D)				2020-7-28
	电子书	电子书：工业机器人设计工程师指南		英语版		2020-3-25
	用户指南	AM335x and AMIC110 Sitara™ Processors Technical Reference Manual (Rev. Q)				2019-12-13
	应用手册	AM335x EMIF Tools				2019-9-20
	用户指南	Powering AMIC110, AMIC120, AM335x, and AM437x with TPS65216	PDF \| HTML			2019-4-11
	白皮书	Ensuring real-time predictability (Rev. B)				2018-12-4
	应用手册	PRU-ICSS EtherCAT Slave Troubleshooting Guide				2018-11-7
	用户指南	Powering the AM335x With the TPS650250 (Rev. B)				2018-3-14
	技术文章	Delivering power to the industrial market with Ethernet	PDF \| HTML			2018-3-8
	技术文章	EtherCAT connectivity without DDR	PDF \| HTML			2018-1-30
	技术文章	Real-time control meets real-time industrial communications development – part two	PDF \| HTML			2017-12-13
	技术文章	New industrial Ethernet protocol: CC-Link IE Field Basic	PDF \| HTML			2017-9-29
	技术文章	Reducing factory downtime with predictive maintenance for industrial Ethernet	PDF \| HTML			2017-9-7
	白皮书	Connected sensors in industrial automation (Rev. B)				2017-6-22
	技术文章	Making industrial communication easy with AMIC110 SoCs	PDF \| HTML			2017-6-6
	技术文章	How to select the right industrial Ethernet standard: PROFIBUS	PDF \| HTML			2016-9-27
	技术文章	Start designing your next Sitara™ processor solution!	PDF \| HTML			2016-7-28
	技术文章	Expanding industrial communication development	PDF \| HTML			2016-5-9

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调试探针

TMDSEMU110-U — XDS110 JTAG 调试探针

德州仪器 (TI) 的 XDS110 是一款适用于 TI 嵌入式处理器的新型调试探针（仿真器）。XDS110 取代了 XDS100 系列，同时在单个仓体中支持更广泛的标准（IEEE1149.1、IEEE1149.7、SWD）。此外，对于带有嵌入式缓冲跟踪器 (ETB) 的所有 Arm® 和 DSP 处理器，所有 XDS 调试探针均支持核心和系统跟踪。对于引脚上的内核跟踪，则需要使用 XDS560v2 PRO TRACE。

德州仪器 (TI) 的 XDS110 通过 TI 20 引脚连接器（带有适合 TI 14 引脚、Arm 10 引脚和 Arm 20 引脚的多个适配器）连接到目标板，通过 (...)

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调试探针

TMDSEMU560V2STM-U — XDS560™ 软件 v2 系统跟踪 USB 调试探针

XDS560v2 是 XDS560™ 系列调试探针中性能最高的一款，同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。请注意，它不支持串行线调试 (SWD)。

对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS 调试探针均支持核心和系统跟踪。对于引脚上的跟踪，则需要使用 XDS560v2 PRO TRACE。

XDS560v2 通过 MIPI HSPT 60 引脚连接器（带有多个用于 TI 14 引脚、TI 20 引脚和 ARM 20 引脚的适配器）连接到目标板，并通过 USB2.0 高速 (...)

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调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针（仿真器）的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款，同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件，通过捕获相关器件级信息，获得准确的总线性能活动和吞吐量，并对内核和外设进行电源管理。此外，对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS (...)

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软件开发套件 (SDK)

PROCESSOR-SDK-AMIC110 — 适用于 AMIC110 Sitara 处理器的处理器 SDK – TI-RTOS 支持

Processor SDK（软件开发套件）是统一的软件平台，适用于 TI 嵌入式处理器，设置简单，提供开箱即用的快速基准测试和演示。 Processor SDK 的所有版本在 TI 的广泛产品系列中保持一致，让开发人员可以无缝地在多种器件之间重用和迁移软件。借助 Processor SDK 和 TI 的嵌入式处理器解决方案，开发可扩展平台解决方案从未如此简单。

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软件开发套件 (SDK)

PROCESSOR-SDK-RTOS-AM335X — 适用于 AM335x 和 AMIC110 器件的 RTOS 处理器 SDK

Processor SDK（软件开发套件）是统一的软件平台，适用于 TI 嵌入式处理器，设置简单，提供开箱即用的基准测试和演示。Processor SDK 的所有版本在 TI 的广泛产品系列中保持一致，让开发人员可以无缝地在多种器件之间重用和迁移软件。Processor SDK 和 TI 的嵌入式处理器解决方案让可扩展平台解决方案的开发变得前所未有的简单。

Processor SDK v.02.xx 包括对 Linux TI-RTOS 操作系统的支持。

Linux 亮点：

长期稳定 (LTS) 主线 Linux 内核支持
U-Boot 引导加载程序支持
Linaro GNU Compiler (...)

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IDE、配置、编译器或调试器

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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IDE、配置、编译器或调试器

SYSCONFIG — Standalone desktop version of SysConfig

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

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线上培训

BOOTL-3P-TRAINING — 适用于 TI 基于 Arm 的处理器的嵌入式软件开发培训

来源：Bootlin

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