ZHCSJB4D April   2019  – January 2024 TAS2563

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  I2C Timing Requirements
    7. 5.7  SPI Timing Requirements
    8. 5.8  PDM Port Timing Requirements
    9. 5.9  TDM Port Timing Requirements
    10. 5.10 Timing Diagrams
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PurePath Console 3 Software
      2. 7.3.2  Device Mode and Address Selection
      3. 7.3.3  General I2C Operation
      4. 7.3.4  General SPI Operation
      5. 7.3.5  Single-Byte and Multiple-Byte Transfers
      6. 7.3.6  Single-Byte Write
      7. 7.3.7  Multiple-Byte Write and Incremental Multiple-Byte Write
      8. 7.3.8  Single-Byte Read
      9. 7.3.9  Multiple-Byte Read
      10. 7.3.10 Register Organization
      11. 7.3.11 Operational Modes
        1. 7.3.11.1 Hardware Shutdown
        2. 7.3.11.2 Software Shutdown
        3. 7.3.11.3 Mute
        4. 7.3.11.4 Active
        5. 7.3.11.5 Perform Load Diagnostics
        6. 7.3.11.6 Mode Control and Software Reset
      12. 7.3.12 Faults and Status
      13. 7.3.13 Digital Input Pull Downs
    4. 7.4 Device Functional Modes
      1. 7.4.1 PDM Input
      2. 7.4.2 TDM Port
      3. 7.4.3 Playback Signal Path
        1. 7.4.3.1 Digital Signal Processor
        2. 7.4.3.2 High Pass Filter
        3. 7.4.3.3 Digital Volume Control and Amplifier Output Level
        4. 7.4.3.4 Auto-mute During Idle Channel Mode
        5. 7.4.3.5 Auto-start/stop on Audio Clocks
        6. 7.4.3.6 Supply Tracking Limiters with Brown Out Prevention
        7. 7.4.3.7 Class-D Settings
      4. 7.4.4 SAR ADC
      5. 7.4.5 Boost
      6. 7.4.6 IV Sense
      7. 7.4.7 Load Diagnostics
      8. 7.4.8 Clocks and PLL
      9. 7.4.9 Thermal Foldback
    5. 7.5 Register Maps
      1. 7.5.1  Register Summary Table Page=0x00
      2. 7.5.2  PAGE (page=0x00 address=0x00) [reset=0h]
      3. 7.5.3  SW_RESET (page=0x00 address=0x01) [reset=0h]
      4. 7.5.4  PWR_CTL (page=0x00 address=0x02) [reset=Eh]
      5. 7.5.5  PB_CFG1 (page=0x00 address=0x03) [reset=20h]
      6. 7.5.6  MISC_CFG1 (page=0x00 address=0x04) [reset=C6h]
      7. 7.5.7  MISC_CFG2 (page=0x00 address=0x05) [reset=22h]
      8. 7.5.8  TDM_CFG0 (page=0x00 address=0x06) [reset=9h]
      9. 7.5.9  TDM_CFG1 (page=0x00 address=0x07) [reset=2h]
      10. 7.5.10 TDM_CFG2 (page=0x00 address=0x08) [reset=4Ah]
      11. 7.5.11 TDM_CFG3 (page=0x00 address=0x09) [reset=10h]
      12. 7.5.12 TDM_CFG4 (page=0x00 address=0x0A) [reset=13h]
      13. 7.5.13 TDM_CFG5 (page=0x00 address=0x0B) [reset=2h]
      14. 7.5.14 TDM_CFG6 (page=0x00 address=0x0C) [reset=0h]
      15. 7.5.15 TDM_CFG7 (page=0x00 address=0x0D) [reset=4h]
      16. 7.5.16 TDM_CFG8 (page=0x00 address=0x0E) [reset=5h]
      17. 7.5.17 TDM_CFG9 (page=0x00 address=0x0F) [reset=6h]
      18. 7.5.18 TDM_CFG10 (page=0x00 address=0x10) [reset=7h]
      19. 7.5.19 DSP Mode & TDM_DET (page=0x00 address=0x11) [reset=7Fh]
      20. 7.5.20 LIM_CFG0 (page=0x00 address=0x12) [reset=12h]
      21. 7.5.21 LIM_CFG1 (page=0x00 address=0x13) [reset=76h]
      22. 7.5.22 DSP FREQUENCY & BOP_CFG0 (page=0x00 address=0x14) [reset=1h]
      23. 7.5.23 BOP_CFG0 (page=0x00 address=0x15) [reset=2Eh]
      24. 7.5.24 BIL_and_ICLA_CFG0 (page=0x00 address=0x16) [reset=60h]
      25. 7.5.25 BIL_ICLA_CFG1 (page=0x00 address=0x17) [reset=0h]
      26. 7.5.26 GAIN_ICLA_CFG0 (page=0x00 address=0x18) [reset=0h]
      27. 7.5.27 ICLA_CFG1 (page=0x00 address=0x19) [reset=0h]
      28. 7.5.28 INT_MASK0 (page=0x00 address=0x1A) [reset=FCh]
      29. 7.5.29 INT_MASK1 (page=0x00 address=0x1B) [reset=A6h]
      30. 7.5.30 INT_MASK2 (page=0x00 address=0x1C) [reset=DFh]
      31. 7.5.31 INT_MASK3 (page=0x00 address=0x1D) [reset=FFh]
      32. 7.5.32 INT_LIVE0 (page=0x00 address=0x1F) [reset=0h]
      33. 7.5.33 INT_LIVE1 (page=0x00 address=0x20) [reset=0h]
      34. 7.5.34 INT_LIVE3 (page=0x00 address=0x21) [reset=0h]
      35. 7.5.35 INT_LIVE4 (page=0x00 address=0x22) [reset=0h]
      36. 7.5.36 INT_LTCH0 (page=0x00 address=0x24) [reset=0h]
      37. 7.5.37 INT_LTCH1 (page=0x00 address=0x25) [reset=0h]
      38. 7.5.38 INT_LTCH3 (page=0x00 address=0x26) [reset=0h]
      39. 7.5.39 INT_LTCH4 (page=0x00 address=0x27) [reset=0h]
      40. 7.5.40 VBAT_MSB (page=0x00 address=0x2A) [reset=0h]
      41. 7.5.41 VBAT_LSB (page=0x00 address=0x2B) [reset=0h]
      42. 7.5.42 TEMP (page=0x00 address=0x2C) [reset=0h]
      43. 7.5.43 INT & CLK CFG (page=0x00 address=0x30) [reset=19h]
      44. 7.5.44 DIN_PD (page=0x00 address=0x31) [reset=40h]
      45. 7.5.45 MISC (page=0x00 address=0x32) [reset=80h]
      46. 7.5.46 BOOST_CFG1 (page=0x00 address=0x33) [reset=34h]
      47. 7.5.47 BOOST_CFG2 (page=0x00 address=0x34) [reset=4Bh]
      48. 7.5.48 BOOST_CFG3 (page=0x00 address=0x35) [reset=74h]
      49. 7.5.49 MISC (page=0x00 address=0x3B) [reset=58h]
      50. 7.5.50 TG_CFG0 (page=0x00 address=0x3F) [reset=0h]
      51. 7.5.51 BST_ILIM_CFG0 (page=0x00 address=0x40) [reset=36h]
      52. 7.5.52 PDM_CONFIG0 (page=0x00 address=0x41) [reset=1h]
      53. 7.5.53 DIN_PD & PDM_CONFIG3 (page=0x00 address=0x42) [reset=F8h]
      54. 7.5.54 ASI2_CONFIG0 (page=0x00 address=0x43) [reset=8h]
      55. 7.5.55 ASI2_CONFIG1 (page=0x00 address=0x44) [reset=0h]
      56. 7.5.56 ASI2_CONFIG2 (page=0x00 address=0x45) [reset=1h]
      57. 7.5.57 ASI2_CONFIG3 (page=0x00 address=0x46) [reset=FCh]
      58. 7.5.58 PVDD_MSB_DSP (page=0x00 address=0x49) [reset=0h]
      59. 7.5.59 PVDD_LSB_DSP (page=0x00 address=0x4A) [reset=0h]
      60. 7.5.60 REV_ID (page=0x00 address=0x7D) [reset=0h]
      61. 7.5.61 I2C_CKSUM (page=0x00 address=0x7E) [reset=0h]
      62. 7.5.62 BOOK (page=0x00 address=0x7F) [reset=0h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 Boost Converter Passive Devices
        3. 8.2.2.3 EMI Passive Devices
        4. 8.2.2.4 Miscellaneous Passive Devices
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
    1. 9.1 Power Supplies
    2. 9.2 Power Supply Sequencing
      1. 9.2.1 Boost Supply Details
      2. 9.2.2 External Boost Mode (Boost Bypass Mode)
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

TA = 25 °C, VBAT = 3.6 V, (External PVDD = 12 V), VDD = 1.8 V, RL = 8Ω + 33 µH, fin = 1 kHz, SSM, fs = 48 kHz, Gain = 16 dBV (External PVDD Gain=18 dBV), SDZ = 1, Thermal Foldback Disabled, Measured filter free with an Audio Precision with a 22 Hz to 20 kHz un-weighted bandwidth (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUT
and OUTPUT
VIH High-level digital input logic voltage threshold (max current limit = 30 mA) All digital pins except SDA_MOSI and SCL_SELZ 0.65 × IOVDD V
VIL Low-level digital input logic voltage threshold (max current limit = 30 mA) All digital pins except SDA_MOSI and SCL_SELZ 0.35 × IOVDD V
VIH(I2C) High-level digital input logic voltage threshold (max current limit = 30 mA)  SDA_MOSI and SCL_SELZ 0.7 × IOVDD V
VIL(I2C) Low-level digital input logic voltage threshold (max current limit = 30 mA) SDA_MOSI and SCL_SELZ 0.3 × IOVDD V
VOH High-level digital output voltage (max current limit = 30 mA) All digital pins except SDA_MOSI ,SCL_SELZ and IRQZ; IOH = 2 mA. IOVDD – 0.45 V V
VOL Low-level digital output voltage (max current limit = 30 mA) All digital pins except SDA_MOSI ,SCL_SELZ and IRQZ; IOL = –2 mA. 0.45 V
VOL(I2C) Low-level digital output voltage (max current limit = 30 mA) SDA and SCL; IOL(I2C) = –2 mA. 0.2 × IOVDD V
VOL(IRQZ) Low-level digital output voltage for IRQZ open drain Output (max current limit = 30 mA) IRQZ; IOL(IRQZ) = –2 mA. 0.45 V
IIH Input logic-high leakage for digital inputs All digital pins; Input = VDD. –5 0.1 5 µA
IIL Input logic-low leakage for digital inputs  All digital pins; Input = GND. –5 0.1 5 µA
CIN Input capacitance for digital inputs  All digital pins 8 pF
RPD Pull down resistance for digital input/IO pins when asserted on SDOUT, SDIN, FSYNC, SBCLK 50 kΩ
AMPLIFIER PERFORMANCE - Internal Boost
Output Voltage for Full-scale digital Input Measured at -6 dB FS input 6.32 Vrms
POUT Maximum Continuous Output Power RL = 32Ω + 33 µH, THD+N = 0.03 %, fin = 1 kHz 1.25 W
RL = 8 Ω + 33 µH, THD+N = 0.03 %, fin = 1 kHz 5 W
RL = 4 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz 6.1 W
System efficiency at POUT = 1 W RL = 8 Ω + 33 µH, fin = 1 kHz 82 %
RL = 4 Ω + 33 µH, fin = 1 kHz 78.5 %
RL = 8 Ω + 33 µH, fin = 1 kHz, VBAT = 4.2 V 82.5 %
RL = 4 Ω + 33 µH, fin = 1 kHz, VBAT = 4.2 V 84.2 %
System efficiency at POUT =0.5 W RL = 8 Ω + 33 µH, fin = 1 kHz 76.6 %
RL = 4 Ω + 33 µH, fin = 1 kHz 81.1 %
RL = 8 Ω + 33 µH, fin = 1 kHz, VBAT = 4.2 V 84.2 %
RL = 4 Ω + 33 µH, fin = 1 kHz, VBAT = 4.2 V 81.6 %
System efficiency at 0.1% THD+N power level RL = 32 Ω + 33 µH, POUT = TBD W, fin = 1 kHz, 78.8 %
RL = 8 Ω + 33 µH, POUT = TBD W, fin = 1 kHz, 80 %
RL = 4 Ω + 33 µH, POUT = TBD W, fin = 1 kHz 76.2 %
THD+N Total harmonic distortion + noise POUT = 0.25 W, RL = 32Ω + 33 µH, fin = 1 kHz 0.01 %
POUT = 1 W, RL = 8 Ω + 33 µH, fin = 1 kHz 0.01 %
POUT = 1 W, RL = 4 Ω + 33 µH, fin = 1 kHz 0.01 %
VN Idle channel noise A-Weighted, 20 Hz - 20 kHz, DAC Modulator Running 14.8 µV
FPWM Class-D PWM switching frequency Average frequency in Spread Spectrum Mode, CLASSD_SYNC=0 384 kHz
Fixed Frequency Mode, CLASSD_SYNC=0 384 kHz
Fixed Frequency Mode, CLASSD_SYNC=1, fs = 44.1, 88.2, 174.6 kHz 352.8 kHz
Fixed Frequency Mode, CLASSD_SYNC=1, fs = 48, 96, 192 kHz 384 kHz
VOS Output offset voltage -1 1 mV
DNR Dynamic range A-Weighted, -60 dBFS Method 105 dB
SNR Signal to noise ratio A-Weighted, Referenced to 1 % THD+N Output Level 112.5 dB
KCP Click and pop performance Into and out of Mute, Shutdown, Power Up, Power Down and audio clocks starting and stopping. Measured with APx Plugin. 3.4 mV
Programmable output level range 8 18 dBV
Programmable output level step size 0.5 dB
AVERROR Amplifier gain error POUT = 1 W ±0.1 dB
Mute attenuation Device in Shutdown or Muted in Normal Operation 110 dB
VBAT power-supply rejection ratio VBAT = 3.6 V + 200 mVpp, fripple = 217 Hz 108 dB
VBAT = 3.6 V + 200 mVpp, fripple = 20 kHz 90 dB
AVDD power-supply rejection ratio VDD = 1.8 V + 200 mVpp, fripple = 217 Hz 98 dB
VDD = 1.8 V + 200 mVpp, fripple = 20 kHz 93 dB
Turn on time from release of SW shutdown No Volume Ramping 1.8 ms
Volume Ramping 4.5 ms
Turn off time from assertion of SW shutdown to amp Hi-Z No Volume Ramping 1.5 ms
Volume Ramping 12.5 ms
AMPLIFIER PERFORMANCE - External PVDD
Output Voltage for Full-scale digital Input Measured at -6 dB FS input 7.94 Vrms
POUT Maximum Continuous Output Power RL = 32Ω + 33 µH, THD+N = 1 %, fin = 1 kHz 1.3 W
RL = 8 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz 5.2 W
RL = 4 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz 10.4 W
RL = 32Ω + 33 µH, THD+N = 10 %, fin = 1 kHz 1.6 W
RL = 8 Ω + 33 µH, THD+N = 10 %, fin = 1 kHz 6.3 W
RL = 4 Ω + 33 µH, THD+N = 10%, fin = 1 kHz 12.6 W
System efficiency at POUT = 1 W RL = 8 Ω + 33 µH, fin = 1 kHz 83.8 %
RL = 4 Ω + 33 µH, fin = 1 kHz 80 %
RL = 8 Ω + 33 µH, fin = 1 kHz, External PVDD = 8.4 V 85.9 %
RL = 4 Ω + 33 µH, fin = 1 kHz,  External PVDD = 8.4 V 81.8 %
System efficiency at 0.1% THD+N power level RL = 32 Ω + 33 µH, POUT = TBD W, fin = 1 kHz, 87.4 %
RL = 8 Ω + 33 µH, POUT = TBD W, fin = 1 kHz, 90 %
RL = 4 Ω + 33 µH, POUT = TBD W, fin = 1 kHz 85.2 %
RL = 32 Ω + 33 µH, POUT = TBD W, fin = 1 kHz, External PVDD = 8.4 V 81.9 %
RL = 8 Ω + 33 µH, POUT = TBD W, fin = 1 kHz, External PVDD = 8.4 V 90 %
RL = 4 Ω + 33 µH, POUT = TBD W, fin = 1 kHz, External PVDD = 8.4 V 86 %
THD+N Total harmonic distortion + noise POUT = 0.25 W, RL = 32Ω + 33 µH, fin = 1 kHz 0.01 %
POUT = 1 W, RL = 8 Ω + 33 µH, fin = 1 kHz 0.01 %
POUT = 1 W, RL = 4 Ω + 33 µH, fin = 1 kHz 0.02 %
VN Idle channel noise A-Weighted, 20 Hz - 20 kHz, DAC Modulator Running 21.3 µV
FPWM Class-D PWM switching frequency Average frequency in Spread Spectrum Mode, CLASSD_SYNC=0 384 kHz
Fixed Frequency Mode, CLASSD_SYNC=0 384 kHz
Fixed Frequency Mode, CLASSD_SYNC=1, fs = 44.1, 88.2, 174.6 kHz 352.8 kHz
Fixed Frequency Mode, CLASSD_SYNC=1, fs = 48, 96, 192 kHz 384 kHz
VOS Output offset voltage -1 1 mV
DNR Dynamic range A-Weighted, -60 dBFS Method 105 dB
SNR Signal to noise ratio A-Weighted, Referenced to 1 % THD+N Output Level 109.5 dB
KCP Click and pop performance Into and out of Mute, Shutdown, Power Up, Power Down and audio clocks starting and stopping. Measured with APx Plugin. 3 mV
Programmable output level range 8 18 dBV
Programmable output level step size 0.5 dB
AVERROR Amplifier gain error POUT = 1 W ±0.1 dB
Mute attenuation Device in Shutdown or Muted in Normal Operation 110 dB
VBAT power-supply rejection ratio VBAT = 3.6 V + 200 mVpp, fripple = 217 Hz 110 dB
VBAT = 3.6 V + 200 mVpp, fripple = 20 kHz 90 dB
PVDD power-supply rejection ratio PVDD = 12 V + 200 mVpp, fripple = 217 Hz 105 dB
PVDD = 12 V + 200 mVpp, fripple = 20 kHz 90 dB
AVDD power-supply rejection ratio VDD = 1.8 V + 200 mVpp, fripple = 217 Hz 86 dB
VDD = 1.8 V + 200 mVpp, fripple = 20 kHz 73 dB
Turn on time from release of SW shutdown No Volume Ramping 2 ms
Volume Ramping 4.8 ms
Turn off time from assertion of SW shutdown to amp Hi-Z No Volume Ramping 1.08 ms
Volume Ramping 12.58 ms
BOOST
CONVERTER
Startup inrush current limit default setting 1.5 A
Startup inrush limit time default setting 0.45 ms
Switching Frequency PFM mode 50 kHz
Current Control Mode 4 MHz
Inductor Peak Current Limit default setting 4 A
DIE TEMPERATURE
SENSOR
Resolution 8 bits
Die temperature measurement range -40 150 °C
Die temperature resolution 0.75 °C
Die temperature accuracy ±5 °C
VOLTAGE
MONITOR
Resolution 10 bits
VBAT measurement range 2 6 V
VBAT resolution 6 mV
VBAT accuracy ±25 mV
PDM INPUT PORT
SNR Signal to Noise Ratio No signal, Input generated using a 4th order PDM modulator 118 dB
No signal, Input generated using a 5th order PDM modulator 128
DR Dynamic Range 20Hz to 20kHz, -60dBFS input signal, A-weighted, Input generated using a 4th order PDM modulator 117 dB
20Hz to 20kHz, -60dBFS input signal, A-weighted, Input generated using a 5th order PDM modulator 127
FR Frequency Response 20Hz to 20kHz -0.1 0 dB
GD Group Delay Input signal fs/50 TBD FSYNC Cycles
TDM SERIAL AUDIO
PORT
PCM Sample Rates & FSYNC Input Frequency 8 96 kHz
SBCLK Input Frequency I2S/TDM Operation 0.512 24.57 MHz
SBCLK Maximum Input Jitter RMS Jitter below 40 kHz that can be tolerated without performance degradation 1 ns
RMS Jitter above 40 kHz that can be tolerated without performance degradation 10 ns
SBCLK Cycles per FSYNC in I2S and TDM Modes Values: 64, 96, 128, 192, 256, 384 and 512 64 512 Cycles
PCM PLAYBACK
CHARACTERISTICS to fs ≤ 48 kHz
fs Sample Rates 8 48 kHz
Passband LPF Corner 0.454 fs
Passband Ripple 20 Hz to LPF cutoff -0.3 0.3 dB
Stop Band Attenuation ≥ 0.55 fs 60 dB
≥ 1 fs 65 dB
Group Delay (ROM MODE) DC to 0.454 fs 38 1/fs
Group Delay (RAM Mode) DC to 0.454 fs TBD 1/fs
PCM PLAYBACK
CHARACTERISTICS fs > 48 kHz
fs Sample Rates 88.2 96 kHz
Passband LPF Corner fs = 96 kHz 0.42 fs
fs = 192 kHz 0.21 fs
Passband Ripple DC to LPF cutoff -0.5 0.5 dB
Stop Band Attenuation ≥ 0.55 fs 60 dB
≥ 1 fs 65 dB
Group Delay (RAM Mode) DC to 0.375 fs for 96 kHz TBD 1/fs
CURRENT
SENSE
DNR Dynamic range Un-Weighted, Relative to 0 dBFS 69 dB
THD+N Total harmonic distortion + noise RL = 8 Ω + 33 µH, fin = 1 kHz, POUT = 1 W -56 dB
RL = 4 Ω + 33 µH, fin = 1 kHz, POUT = 1 W -57 dB
Full-scale input current 2.0 A
Current-sense accuracy RL = 8 Ω + 33 µH, IOUT = 354 mARMS (POUT = 1 W @ 1kHz) ±1 %
Current-sense gain error over temperature 0°C to 70°C, 8 Ω, using a 60Hz -40dB pilot tone ±1 %
Current-sense gain error over output power 50mW to 0.1 % THD+N level, fin = 1 kHz, 8 Ω, using a 60Hz -40dB pilot tone ±1.5 %
LPF passband corner fs = 8 kHz to 48 kHz 0.417 fs
fs = 88.2 kHz 0.208 fs
fs = 96 kHz 0.208 fs
LPF passband ripple -0.05 0.05 dB
LPF stopband attenuation 0.55 fs 60 dB
VOLTAGE
SENSE
DNR Dynamic range Un-Weighted, Relative 0 dBFS 69 dB
THD+N Total harmonic distortion + noise RL = 8 Ω + 33 µH, fin = 1 kHz, POUT = 1W -60 dB
RL = 4 Ω + 33 µH, fin = 1 kHz, POUT = 1W -60 dB
Full-scale input voltage 14 VPK
Voltage-sense accuracy RL = 8 Ω + 33 µH, IOUT = 354 mARMS (POUT = 1 W) ±0.5%
Voltage-sense gain error over temperature 0°C to 70°C, 8 Ω, using a 60Hz -40dB pilot tone ±0.5%
Voltage-sense gain error over output power 50mV to 0.1 % THD+N level, 8 Ω, using a 60Hz -40dB pilot tone ±0.5%
LPF passband corner fs = 14.7 kHz to 48 kHz 0.417 fs
fs = 88.2 kHz 0.208 fs
fs = 96 kHz 0.208 fs
LPF passband ripple -0.05 0.05 dB
LPF stopband attenuation 0.55 fs 60 dB
VOLTAGE/CURRENT
SENSE RATIO
Gain ratio error over output power 50mW to 0.1 % THD+N level, fin = 1 kHz, 8Ω, using a 60Hz -40dB pilot tone ±1%
Gain ratio drift over temperature 0°C to 70°C ±1%
V/I phase error 300 ns
TYPICAL CURRENT
CONSUMPTION
Current consumption in hardware shutdown SDZ = 0, VBAT 1 µA
SDZ = 0, VDD 1 µA
Current consumption in software shutdown All Clocks Stopped, VBAT 1 µA
All Clocks Stopped, VDD 10 µA
Current consumption in idle channel Clocking 0s PCM mode, VBAT 2.7 mA
Clocking 0s PCM mode, VDD, DSBGA Package 10.9 mA
Clocking 0s PCM mode, VDD, QFN Package 11.7 mA
Current consumption during active operation with IV sense disabled fs = 48 kHz, VBAT 4.6 mA
fs = 48 kHz, VDD, DSBGA Package 10.9 mA
fs = 48 kHz, VDD, QFN Package 11.7 mA
Current consumption during active operation with IV sense enabled fs = 48 kHz, VBAT 4.6 mA
fs = 48 kHz, VDD, DSBGA Package 12.5 mA
fs = 48 kHz, VDD, QFN Package 13.3 mA
PROTECTION
CIRCUITRY
Thermal shutdown temperature 140 °C
Thermal shutdown retry 1.5 s
VBAT undervoltage lockout threshold (UVLO) UVLO is asserted 2 V
UVLO is released 2.55 V
Output short circuit limit Output to Output, Output to GND, Output to VBST or Output to VBAT Short 3.75 A