ZHCSJ34F
December 2015 – May 2019
PRODUCTION DATA.
1
器件概述
1.1
特性
1.2
应用
1.3
说明
1.4
功能方框图
2
修订历史记录
3
Device Comparison
3.1
Related Products
4
Terminal Configuration and Functions
4.1
Terminal Assignment
4.1.1
Unused Balls Connection Requirements
4.2
Ball Characteristics
4.3
Multiplexing Characteristics
4.4
Signal Descriptions
4.4.1
Video Input Port (VIP)
4.4.2
Display Subsystem – Video Output Ports
4.4.3
Display Subsystem – High-Definition Multimedia Interface (HDMI)
4.4.4
External Memory Interface (EMIF)
4.4.5
General-Purpose Memory Controller (GPMC)
4.4.6
Timers
4.4.7
Inter-Integrated Circuit Interface (I2C)
4.4.8
Universal Asynchronous Receiver Transmitter (UART)
4.4.9
Multichannel Serial Peripheral Interface (McSPI)
4.4.10
Quad Serial Peripheral Interface (QSPI)
4.4.11
Multichannel Audio Serial Port (McASP)
4.4.12
Universal Serial Bus (USB)
4.4.13
SATA
4.4.14
Peripheral Component Interconnect Express (PCIe)
4.4.15
Controller Area Network Interface (DCAN)
4.4.16
Ethernet Interface (GMAC_SW)
4.4.17
eMMC/SD/SDIO
4.4.18
General-Purpose Interface (GPIO)
4.4.19
Pulse Width Modulation (PWM) Interface
4.4.20
System and Miscellaneous
4.4.20.1
Sysboot Interface
4.4.20.2
Power, Reset, and Clock Management (PRCM)
4.4.20.3
Real Time Clock (RTC) Interface
4.4.20.4
System Direct Memory Access (SDMA)
4.4.20.5
Interrupt Controllers (INTC)
4.4.20.6
Observability
4.4.20.7
Power Supplies
4.4.21
Test Interfaces
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Power on Hour (POH) Limits
5.4
Recommended Operating Conditions
5.5
Operating Performance Points
5.5.1
AVS and ABB Requirements
5.5.2
Voltage And Core Clock Specifications
5.5.3
Maximum Supported Frequency
5.6
Power Consumption Summary
5.7
Electrical Characteristics
5.7.1
LVCMOS DDR DC Electrical Characteristics
5.7.2
HDMIPHY DC Electrical Characteristics
5.7.3
Dual Voltage LVCMOS I2C DC Electrical Characteristics
5.7.4
IQ1833 Buffers DC Electrical Characteristics
5.7.5
IHHV1833 Buffers DC Electrical Characteristics
5.7.6
LVCMOS OSC Buffers DC Electrical Characteristics
5.7.7
BC1833IHHV Buffers DC Electrical Characteristics
5.7.8
USBPHY DC Electrical Characteristics
5.7.9
Dual Voltage SDIO1833 DC Electrical Characteristics
5.7.10
Dual Voltage LVCMOS DC Electrical Characteristics
5.7.11
SATAPHY DC Electrical Characteristics
5.7.12
PCIEPHY DC Electrical Characteristics
5.8
Thermal Resistance Characteristics
5.8.1
Package Thermal Characteristics
5.9
Power Supply Sequences
6
Clock Specifications
6.1
Input Clock Specifications
6.1.1
Input Clock Requirements
6.1.2
System Oscillator OSC0 Input Clock
6.1.2.1
OSC0 External Crystal
6.1.2.2
OSC0 Input Clock
6.1.3
Auxiliary Oscillator OSC1 Input Clock
6.1.3.1
OSC1 External Crystal
6.1.3.2
OSC1 Input Clock
6.1.4
RTC Oscillator Input Clock
6.1.4.1
RTC Oscillator External Crystal
6.1.4.2
RTC Oscillator Input Clock
6.2
RC On-die Oscillator Clock
6.3
DPLLs, DLLs Specifications
6.3.1
DPLL Characteristics
6.3.2
DLL Characteristics
6.3.3
DPLL and DLL Noise Isolation
7
Timing Requirements and Switching Characteristics
7.1
Timing Test Conditions
7.2
Interface Clock Specifications
7.2.1
Interface Clock Terminology
7.2.2
Interface Clock Frequency
7.3
Timing Parameters and Information
7.3.1
Parameter Information
7.3.1.1
1.8V and 3.3V Signal Transition Levels
7.3.1.2
1.8V and 3.3V Signal Transition Rates
7.3.1.3
Timing Parameters and Board Routing Analysis
7.4
Recommended Clock and Control Signal Transition Behavior
7.5
Virtual and Manual I/O Timing Modes
7.6
Video Input Ports (VIP)
7.7
Display Subsystem – Video Output Ports
7.8
Display Subsystem – High-Definition Multimedia Interface (HDMI)
7.9
External Memory Interface (EMIF)
7.10
General-Purpose Memory Controller (GPMC)
7.10.1
GPMC/NOR Flash Interface Synchronous Timing
7.10.2
GPMC/NOR Flash Interface Asynchronous Timing
7.10.3
GPMC/NAND Flash Interface Asynchronous Timing
7.11
Timers
7.12
Inter-Integrated Circuit Interface (I2C)
Table 7-34
Timing Requirements for I2C Input Timings
Table 7-35
Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
Table 7-36
Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
7.13
Universal Asynchronous Receiver Transmitter (UART)
Table 7-37
Timing Requirements for UART
Table 7-38
Switching Characteristics Over Recommended Operating Conditions for UART
7.14
Multichannel Serial Peripheral Interface (McSPI)
7.15
Quad Serial Peripheral Interface (QSPI)
7.16
Multichannel Audio Serial Port (McASP)
Table 7-45
Timing Requirements for McASP1
Table 7-46
Timing Requirements for McASP2
Table 7-47
Timing Requirements for McASP3/4/5/6/7/8
Table 7-48
Switching Characteristics Over Recommended Operating Conditions for McASP1
Table 7-49
Switching Characteristics Over Recommended Operating Conditions for McASP2
Table 7-50
Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
7.17
Universal Serial Bus (USB)
7.17.1
USB1 DRD PHY
7.17.2
USB2 PHY
7.17.3
USB3 and USB4 DRD ULPI—SDR—Slave Mode—12-pin Mode
7.18
Serial Advanced Technology Attachment (SATA)
7.19
Peripheral Component Interconnect Express (PCIe)
7.20
Controller Area Network Interface (DCAN)
Table 7-65
Timing Requirements for DCANx Receive
Table 7-66
Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
7.21
Ethernet Interface (GMAC_SW)
7.21.1
GMAC MII Timings
Table 7-67
Timing Requirements for miin_rxclk - MII Operation
Table 7-68
Timing Requirements for miin_txclk - MII Operation
Table 7-69
Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
Table 7-70
Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
7.21.2
GMAC MDIO Interface Timings
7.21.3
GMAC RMII Timings
Table 7-75
Timing Requirements for GMAC REF_CLK - RMII Operation
Table 7-76
Timing Requirements for GMAC RMIIn Receive
Table 7-77
Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
Table 7-78
Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
7.21.4
GMAC RGMII Timings
Table 7-82
Timing Requirements for rgmiin_rxc - RGMIIn Operation
Table 7-83
Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
Table 7-84
Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
Table 7-85
Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
7.22
eMMC/SD/SDIO
7.22.1
MMC1—SD Card Interface
7.22.1.1
Default speed, 4-bit data, SDR, half-cycle
7.22.1.2
High speed, 4-bit data, SDR, half-cycle
7.22.1.3
SDR12, 4-bit data, half-cycle
7.22.1.4
SDR25, 4-bit data, half-cycle
7.22.1.5
UHS-I SDR50, 4-bit data, half-cycle
7.22.1.6
UHS-I SDR104, 4-bit data, half-cycle
7.22.1.7
UHS-I DDR50, 4-bit data
7.22.2
MMC2 — eMMC
7.22.2.1
Standard JC64 SDR, 8-bit data, half cycle
7.22.2.2
High-speed JC64 SDR, 8-bit data, half cycle
7.22.2.3
High-speed HS200 JC64 SDR, 8-bit data, half cycle
7.22.2.4
High-speed JC64 DDR, 8-bit data
7.22.3
MMC3 and MMC4—SDIO/SD
7.22.3.1
MMC3 and MMC4, SD Default Speed
7.22.3.2
MMC3 and MMC4, SD High Speed
7.22.3.3
MMC3 and MMC4, SD and SDIO SDR12 Mode
7.22.3.4
MMC3 and MMC4, SD SDR25 Mode
7.22.3.5
MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
7.23
General-Purpose Interface (GPIO)
7.24
System and Miscellaneous interfaces
7.25
Test Interfaces
7.25.1
IEEE 1149.1 Standard-Test-Access Port (JTAG)
7.25.1.1
JTAG Electrical Data/Timing
Table 7-134
Timing Requirements for IEEE 1149.1 JTAG
Table 7-135
Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
Table 7-136
Timing Requirements for IEEE 1149.1 JTAG With RTCK
Table 7-137
Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
7.25.2
Trace Port Interface Unit (TPIU)
7.25.2.1
TPIU PLL DDR Mode
8
Applications, Implementation, and Layout
8.1
Introduction
8.1.1
Initial Requirements and Guidelines
8.2
Power Optimizations
8.2.1
Step 1: PCB Stack-up
8.2.2
Step 2: Physical Placement
8.2.3
Step 3: Static Analysis
8.2.3.1
PDN Resistance and IR Drop
8.2.4
Step 4: Frequency Analysis
8.2.5
System ESD Generic Guidelines
8.2.5.1
System ESD Generic PCB Guideline
8.2.5.2
Miscellaneous EMC Guidelines to Mitigate ESD Immunity
8.2.6
EMI / EMC Issues Prevention
8.2.6.1
Signal Bandwidth
8.2.6.2
Signal Routing
8.2.6.2.1
Signal Routing—Sensitive Signals and Shielding
8.2.6.2.2
Signal Routing—Outer Layer Routing
8.2.6.3
Ground Guidelines
8.2.6.3.1
PCB Outer Layers
8.2.6.3.2
Metallic Frames
8.2.6.3.3
Connectors
8.2.6.3.4
Guard Ring on PCB Edges
8.2.6.3.5
Analog and Digital Ground
8.3
Core Power Domains
8.3.1
General Constraints and Theory
8.3.2
Voltage Decoupling
8.3.3
Static PDN Analysis
8.3.4
Dynamic PDN Analysis
8.3.5
Power Supply Mapping
8.3.6
DPLL Voltage Requirement
8.3.7
Loss of Input Power Event
8.3.8
Example PCB Design
8.3.8.1
Example Stack-up
8.3.8.2
vdd_mpu Example Analysis
8.4
Single-Ended Interfaces
8.4.1
General Routing Guidelines
8.4.2
QSPI Board Design and Layout Guidelines
8.5
Differential Interfaces
8.5.1
General Routing Guidelines
8.5.2
USB 2.0 Board Design and Layout Guidelines
8.5.2.1
Background
8.5.2.2
USB PHY Layout Guide
8.5.2.2.1
General Routing and Placement
8.5.2.2.2
Specific Guidelines for USB PHY Layout
8.5.2.2.2.1
Analog, PLL, and Digital Power Supply Filtering
8.5.2.2.2.2
Analog, Digital, and PLL Partitioning
8.5.2.2.2.3
Board Stackup
8.5.2.2.2.4
Cable Connector Socket
8.5.2.2.2.5
Clock Routings
8.5.2.2.2.6
Crystals/Oscillator
8.5.2.2.2.7
DP/DM Trace
8.5.2.2.2.8
DP/DM Vias
8.5.2.2.2.9
Image Planes
8.5.2.2.2.10
JTAG Interface
8.5.2.2.2.11
Power Regulators
8.5.2.3
Electrostatic Discharge (ESD)
8.5.2.3.1
IEC ESD Stressing Test
8.5.2.3.1.1
Test Mode
8.5.2.3.1.2
Air Discharge Mode
8.5.2.3.1.3
Test Type
8.5.2.3.2
TI Component Level IEC ESD Test
8.5.2.3.3
Construction of a Custom USB Connector
8.5.2.3.4
ESD Protection System Design Consideration
8.5.2.4
References
8.5.3
USB 3.0 Board Design and Layout Guidelines
8.5.3.1
USB 3.0 interface introduction
8.5.3.2
USB 3.0 General routing rules
8.5.4
HDMI Board Design and Layout Guidelines
8.5.4.1
HDMI Interface Schematic
8.5.4.2
TMDS General Routing Guidelines
8.5.4.3
TPD5S115
8.5.4.4
HDMI ESD Protection Device (Required)
8.5.4.5
PCB Stackup Specifications
8.5.4.6
Grounding
8.5.5
SATA Board Design and Layout Guidelines
8.5.5.1
SATA Interface Schematic
8.5.5.2
Compatible SATA Components and Modes
8.5.5.3
PCB Stackup Specifications
8.5.5.4
Routing Specifications
8.5.6
PCIe Board Design and Layout Guidelines
8.5.6.1
PCIe Connections and Interface Compliance
8.5.6.1.1
Coupling Capacitors
8.5.6.1.2
Polarity Inversion
8.5.6.2
Non-standard PCIe connections
8.5.6.2.1
PCB Stackup Specifications
8.5.6.2.2
Routing Specifications
8.5.6.2.2.1
Impedance
8.5.6.2.2.2
Differential Coupling
8.5.6.2.2.3
Pair Length Matching
8.5.6.3
LJCB_REFN/P Connections
8.6
Clock Routing Guidelines
8.6.1
32-kHz Oscillator Routing
8.6.2
Oscillator Ground Connection
8.7
DDR2/DDR3 Board Design and Layout Guidelines
8.7.1
DDR2/DDR3 General Board Layout Guidelines
8.7.2
DDR2 Board Design and Layout Guidelines
8.7.2.1
Board Designs
8.7.2.2
DDR2 Interface
8.7.2.2.1
DDR2 Interface Schematic
8.7.2.2.2
Compatible JEDEC DDR2 Devices
8.7.2.2.3
PCB Stackup
8.7.2.2.4
Placement
8.7.2.2.5
DDR2 Keepout Region
8.7.2.2.6
Bulk Bypass Capacitors
8.7.2.2.7
High-Speed Bypass Capacitors
8.7.2.2.8
Net Classes
8.7.2.2.9
DDR2 Signal Termination
8.7.2.2.10
VREF Routing
8.7.2.3
DDR2 CK and ADDR_CTRL Routing
8.7.3
DDR3 Board Design and Layout Guidelines
8.7.3.1
Board Designs
8.7.3.1.1
DDR3 versus DDR2
8.7.3.2
DDR3 EMIFs
8.7.3.3
DDR3 Device Combinations
8.7.3.4
DDR3 Interface Schematic
8.7.3.4.1
32-Bit DDR3 Interface
8.7.3.4.2
16-Bit DDR3 Interface
8.7.3.5
Compatible JEDEC DDR3 Devices
8.7.3.6
PCB Stackup
8.7.3.7
Placement
8.7.3.8
DDR3 Keepout Region
8.7.3.9
Bulk Bypass Capacitors
8.7.3.10
High-Speed Bypass Capacitors
8.7.3.10.1
Return Current Bypass Capacitors
8.7.3.11
Net Classes
8.7.3.12
DDR3 Signal Termination
8.7.3.13
VREF_DDR Routing
8.7.3.14
VTT
8.7.3.15
CK and ADDR_CTRL Topologies and Routing Definition
8.7.3.15.1
Four DDR3 Devices
8.7.3.15.1.1
CK and ADDR_CTRL Topologies, Four DDR3 Devices
8.7.3.15.1.2
CK and ADDR_CTRL Routing, Four DDR3 Devices
8.7.3.15.2
Two DDR3 Devices
8.7.3.15.2.1
CK and ADDR_CTRL Topologies, Two DDR3 Devices
8.7.3.15.2.2
CK and ADDR_CTRL Routing, Two DDR3 Devices
8.7.3.15.3
One DDR3 Device
8.7.3.15.3.1
CK and ADDR_CTRL Topologies, One DDR3 Device
8.7.3.15.3.2
CK and ADDR/CTRL Routing, One DDR3 Device
8.7.3.16
Data Topologies and Routing Definition
8.7.3.16.1
DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
8.7.3.16.2
DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
8.7.3.17
Routing Specification
8.7.3.17.1
CK and ADDR_CTRL Routing Specification
8.7.3.17.2
DQS and DQ Routing Specification
9
Device and Documentation Support
9.1
Device Nomenclature and Orderable Information
9.1.1
Standard Package Symbolization
9.1.2
Device Naming Convention
9.2
Tools and Software
9.3
Documentation Support
9.4
Related Links
9.5
Community Resources
9.6
商标
9.7
静电放电警告
9.8
Glossary
10
Mechanical, Packaging, and Orderable Information
10.1
Packaging Information
8.7.2
DDR2 Board Design and Layout Guidelines