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  • TDA2x ADAS 应用 处理器 23mm 封装（ABC 封装）器件版本 2.0

    • ZHCSJ34F December   2015  – May 2019 TDA2HF , TDA2HG , TDA2HV , TDA2LF , TDA2SA , TDA2SG , TDA2SX

      PRODUCTION DATA.  

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  • TDA2x ADAS 应用 处理器 23mm 封装（ABC 封装）器件版本 2.0
  1. 1 器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2 修订历史记录
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Terminal Assignment
      1. 4.1.1 Unused Balls Connection Requirements
    2. 4.2 Ball Characteristics
    3. 4.3 Multiplexing Characteristics
    4. 4.4 Signal Descriptions
      1. 4.4.1  Video Input Port (VIP)
      2. 4.4.2  Display Subsystem – Video Output Ports
      3. 4.4.3  Display Subsystem – High-Definition Multimedia Interface (HDMI)
      4. 4.4.4  External Memory Interface (EMIF)
      5. 4.4.5  General-Purpose Memory Controller (GPMC)
      6. 4.4.6  Timers
      7. 4.4.7  Inter-Integrated Circuit Interface (I2C)
      8. 4.4.8  Universal Asynchronous Receiver Transmitter (UART)
      9. 4.4.9  Multichannel Serial Peripheral Interface (McSPI)
      10. 4.4.10 Quad Serial Peripheral Interface (QSPI)
      11. 4.4.11 Multichannel Audio Serial Port (McASP)
      12. 4.4.12 Universal Serial Bus (USB)
      13. 4.4.13 SATA
      14. 4.4.14 Peripheral Component Interconnect Express (PCIe)
      15. 4.4.15 Controller Area Network Interface (DCAN)
      16. 4.4.16 Ethernet Interface (GMAC_SW)
      17. 4.4.17 eMMC/SD/SDIO
      18. 4.4.18 General-Purpose Interface (GPIO)
      19. 4.4.19 Pulse Width Modulation (PWM) Interface
      20. 4.4.20 System and Miscellaneous
        1. 4.4.20.1 Sysboot Interface
        2. 4.4.20.2 Power, Reset, and Clock Management (PRCM)
        3. 4.4.20.3 Real Time Clock (RTC) Interface
        4. 4.4.20.4 System Direct Memory Access (SDMA)
        5. 4.4.20.5 Interrupt Controllers (INTC)
        6. 4.4.20.6 Observability
        7. 4.4.20.7 Power Supplies
      21. 4.4.21 Test Interfaces
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power on Hour (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. 5.7.1  LVCMOS DDR DC Electrical Characteristics
      2. 5.7.2  HDMIPHY DC Electrical Characteristics
      3. 5.7.3  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      4. 5.7.4  IQ1833 Buffers DC Electrical Characteristics
      5. 5.7.5  IHHV1833 Buffers DC Electrical Characteristics
      6. 5.7.6  LVCMOS OSC Buffers DC Electrical Characteristics
      7. 5.7.7  BC1833IHHV Buffers DC Electrical Characteristics
      8. 5.7.8  USBPHY DC Electrical Characteristics
      9. 5.7.9  Dual Voltage SDIO1833 DC Electrical Characteristics
      10. 5.7.10 Dual Voltage LVCMOS DC Electrical Characteristics
      11. 5.7.11 SATAPHY DC Electrical Characteristics
      12. 5.7.12 PCIEPHY DC Electrical Characteristics
    8. 5.8 Thermal Resistance Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Power Supply Sequences
  6. 6 Clock Specifications
    1. 6.1 Input Clock Specifications
      1. 6.1.1 Input Clock Requirements
      2. 6.1.2 System Oscillator OSC0 Input Clock
        1. 6.1.2.1 OSC0 External Crystal
        2. 6.1.2.2 OSC0 Input Clock
      3. 6.1.3 Auxiliary Oscillator OSC1 Input Clock
        1. 6.1.3.1 OSC1 External Crystal
        2. 6.1.3.2 OSC1 Input Clock
      4. 6.1.4 RTC Oscillator Input Clock
        1. 6.1.4.1 RTC Oscillator External Crystal
        2. 6.1.4.2 RTC Oscillator Input Clock
    2. 6.2 RC On-die Oscillator Clock
    3. 6.3 DPLLs, DLLs Specifications
      1. 6.3.1 DPLL Characteristics
      2. 6.3.2 DLL Characteristics
      3. 6.3.3 DPLL and DLL Noise Isolation
  7. 7 Timing Requirements and Switching Characteristics
    1. 7.1  Timing Test Conditions
    2. 7.2  Interface Clock Specifications
      1. 7.2.1 Interface Clock Terminology
      2. 7.2.2 Interface Clock Frequency
    3. 7.3  Timing Parameters and Information
      1. 7.3.1 Parameter Information
        1. 7.3.1.1 1.8V and 3.3V Signal Transition Levels
        2. 7.3.1.2 1.8V and 3.3V Signal Transition Rates
        3. 7.3.1.3 Timing Parameters and Board Routing Analysis
    4. 7.4  Recommended Clock and Control Signal Transition Behavior
    5. 7.5  Virtual and Manual I/O Timing Modes
    6. 7.6  Video Input Ports (VIP)
    7. 7.7  Display Subsystem – Video Output Ports
    8. 7.8  Display Subsystem – High-Definition Multimedia Interface (HDMI)
    9. 7.9  External Memory Interface (EMIF)
    10. 7.10 General-Purpose Memory Controller (GPMC)
      1. 7.10.1 GPMC/NOR Flash Interface Synchronous Timing
      2. 7.10.2 GPMC/NOR Flash Interface Asynchronous Timing
      3. 7.10.3 GPMC/NAND Flash Interface Asynchronous Timing
    11. 7.11 Timers
    12. 7.12 Inter-Integrated Circuit Interface (I2C)
      1. Table 7-34 Timing Requirements for I2C Input Timings
      2. Table 7-35 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
      3. Table 7-36 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
    13. 7.13 Universal Asynchronous Receiver Transmitter (UART)
      1. Table 7-37 Timing Requirements for UART
      2. Table 7-38 Switching Characteristics Over Recommended Operating Conditions for UART
    14. 7.14 Multichannel Serial Peripheral Interface (McSPI)
    15. 7.15 Quad Serial Peripheral Interface (QSPI)
    16. 7.16 Multichannel Audio Serial Port (McASP)
      1. Table 7-45 Timing Requirements for McASP1
      2. Table 7-46 Timing Requirements for McASP2
      3. Table 7-47 Timing Requirements for McASP3/4/5/6/7/8
      4. Table 7-48 Switching Characteristics Over Recommended Operating Conditions for McASP1
      5. Table 7-49 Switching Characteristics Over Recommended Operating Conditions for McASP2
      6. Table 7-50 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
    17. 7.17 Universal Serial Bus (USB)
      1. 7.17.1 USB1 DRD PHY
      2. 7.17.2 USB2 PHY
      3. 7.17.3 USB3 and USB4 DRD ULPI—SDR—Slave Mode—12-pin Mode
    18. 7.18 Serial Advanced Technology Attachment (SATA)
    19. 7.19 Peripheral Component Interconnect Express (PCIe)
    20. 7.20 Controller Area Network Interface (DCAN)
      1. Table 7-65 Timing Requirements for DCANx Receive
      2. Table 7-66 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
    21. 7.21 Ethernet Interface (GMAC_SW)
      1. 7.21.1 GMAC MII Timings
        1. Table 7-67 Timing Requirements for miin_rxclk - MII Operation
        2. Table 7-68 Timing Requirements for miin_txclk - MII Operation
        3. Table 7-69 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
        4. Table 7-70 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
      2. 7.21.2 GMAC MDIO Interface Timings
      3. 7.21.3 GMAC RMII Timings
        1. Table 7-75 Timing Requirements for GMAC REF_CLK - RMII Operation
        2. Table 7-76 Timing Requirements for GMAC RMIIn Receive
        3. Table 7-77 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
        4. Table 7-78 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
      4. 7.21.4 GMAC RGMII Timings
        1. Table 7-82 Timing Requirements for rgmiin_rxc - RGMIIn Operation
        2. Table 7-83 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
        3. Table 7-84 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
        4. Table 7-85 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
    22. 7.22 eMMC/SD/SDIO
      1. 7.22.1 MMC1—SD Card Interface
        1. 7.22.1.1 Default speed, 4-bit data, SDR, half-cycle
        2. 7.22.1.2 High speed, 4-bit data, SDR, half-cycle
        3. 7.22.1.3 SDR12, 4-bit data, half-cycle
        4. 7.22.1.4 SDR25, 4-bit data, half-cycle
        5. 7.22.1.5 UHS-I SDR50, 4-bit data, half-cycle
        6. 7.22.1.6 UHS-I SDR104, 4-bit data, half-cycle
        7. 7.22.1.7 UHS-I DDR50, 4-bit data
      2. 7.22.2 MMC2 — eMMC
        1. 7.22.2.1 Standard JC64 SDR, 8-bit data, half cycle
        2. 7.22.2.2 High-speed JC64 SDR, 8-bit data, half cycle
        3. 7.22.2.3 High-speed HS200 JC64 SDR, 8-bit data, half cycle
        4. 7.22.2.4 High-speed JC64 DDR, 8-bit data
      3. 7.22.3 MMC3 and MMC4—SDIO/SD
        1. 7.22.3.1 MMC3 and MMC4, SD Default Speed
        2. 7.22.3.2 MMC3 and MMC4, SD High Speed
        3. 7.22.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
        4. 7.22.3.4 MMC3 and MMC4, SD SDR25 Mode
        5. 7.22.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
    23. 7.23 General-Purpose Interface (GPIO)
    24. 7.24 System and Miscellaneous interfaces
    25. 7.25 Test Interfaces
      1. 7.25.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
        1. 7.25.1.1 JTAG Electrical Data/Timing
          1. Table 7-134 Timing Requirements for IEEE 1149.1 JTAG
          2. Table 7-135 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
          3. Table 7-136 Timing Requirements for IEEE 1149.1 JTAG With RTCK
          4. Table 7-137 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
      2. 7.25.2 Trace Port Interface Unit (TPIU)
        1. 7.25.2.1 TPIU PLL DDR Mode
  8. 8 Applications, Implementation, and Layout
    1. 8.1 Introduction
      1. 8.1.1 Initial Requirements and Guidelines
    2. 8.2 Power Optimizations
      1. 8.2.1 Step 1: PCB Stack-up
      2. 8.2.2 Step 2: Physical Placement
      3. 8.2.3 Step 3: Static Analysis
        1. 8.2.3.1 PDN Resistance and IR Drop
      4. 8.2.4 Step 4: Frequency Analysis
      5. 8.2.5 System ESD Generic Guidelines
        1. 8.2.5.1 System ESD Generic PCB Guideline
        2. 8.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
      6. 8.2.6 EMI / EMC Issues Prevention
        1. 8.2.6.1 Signal Bandwidth
        2. 8.2.6.2 Signal Routing
          1. 8.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 8.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 8.2.6.3 Ground Guidelines
          1. 8.2.6.3.1 PCB Outer Layers
          2. 8.2.6.3.2 Metallic Frames
          3. 8.2.6.3.3 Connectors
          4. 8.2.6.3.4 Guard Ring on PCB Edges
          5. 8.2.6.3.5 Analog and Digital Ground
    3. 8.3 Core Power Domains
      1. 8.3.1 General Constraints and Theory
      2. 8.3.2 Voltage Decoupling
      3. 8.3.3 Static PDN Analysis
      4. 8.3.4 Dynamic PDN Analysis
      5. 8.3.5 Power Supply Mapping
      6. 8.3.6 DPLL Voltage Requirement
      7. 8.3.7 Loss of Input Power Event
      8. 8.3.8 Example PCB Design
        1. 8.3.8.1 Example Stack-up
        2. 8.3.8.2 vdd_mpu Example Analysis
    4. 8.4 Single-Ended Interfaces
      1. 8.4.1 General Routing Guidelines
      2. 8.4.2 QSPI Board Design and Layout Guidelines
    5. 8.5 Differential Interfaces
      1. 8.5.1 General Routing Guidelines
      2. 8.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 8.5.2.1 Background
        2. 8.5.2.2 USB PHY Layout Guide
          1. 8.5.2.2.1 General Routing and Placement
          2. 8.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 8.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 8.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 8.5.2.2.2.3  Board Stackup
            4. 8.5.2.2.2.4  Cable Connector Socket
            5. 8.5.2.2.2.5  Clock Routings
            6. 8.5.2.2.2.6  Crystals/Oscillator
            7. 8.5.2.2.2.7  DP/DM Trace
            8. 8.5.2.2.2.8  DP/DM Vias
            9. 8.5.2.2.2.9  Image Planes
            10. 8.5.2.2.2.10 JTAG Interface
            11. 8.5.2.2.2.11 Power Regulators
        3. 8.5.2.3 Electrostatic Discharge (ESD)
          1. 8.5.2.3.1 IEC ESD Stressing Test
            1. 8.5.2.3.1.1 Test Mode
            2. 8.5.2.3.1.2 Air Discharge Mode
            3. 8.5.2.3.1.3 Test Type
          2. 8.5.2.3.2 TI Component Level IEC ESD Test
          3. 8.5.2.3.3 Construction of a Custom USB Connector
          4. 8.5.2.3.4 ESD Protection System Design Consideration
        4. 8.5.2.4 References
      3. 8.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 8.5.3.1 USB 3.0 interface introduction
        2. 8.5.3.2 USB 3.0 General routing rules
      4. 8.5.4 HDMI Board Design and Layout Guidelines
        1. 8.5.4.1 HDMI Interface Schematic
        2. 8.5.4.2 TMDS General Routing Guidelines
        3. 8.5.4.3 TPD5S115
        4. 8.5.4.4 HDMI ESD Protection Device (Required)
        5. 8.5.4.5 PCB Stackup Specifications
        6. 8.5.4.6 Grounding
      5. 8.5.5 SATA Board Design and Layout Guidelines
        1. 8.5.5.1 SATA Interface Schematic
        2. 8.5.5.2 Compatible SATA Components and Modes
        3. 8.5.5.3 PCB Stackup Specifications
        4. 8.5.5.4 Routing Specifications
      6. 8.5.6 PCIe Board Design and Layout Guidelines
        1. 8.5.6.1 PCIe Connections and Interface Compliance
          1. 8.5.6.1.1 Coupling Capacitors
          2. 8.5.6.1.2 Polarity Inversion
        2. 8.5.6.2 Non-standard PCIe connections
          1. 8.5.6.2.1 PCB Stackup Specifications
          2. 8.5.6.2.2 Routing Specifications
            1. 8.5.6.2.2.1 Impedance
            2. 8.5.6.2.2.2 Differential Coupling
            3. 8.5.6.2.2.3 Pair Length Matching
        3. 8.5.6.3 LJCB_REFN/P Connections
    6. 8.6 Clock Routing Guidelines
      1. 8.6.1 32-kHz Oscillator Routing
      2. 8.6.2 Oscillator Ground Connection
    7. 8.7 DDR2/DDR3 Board Design and Layout Guidelines
      1. 8.7.1 DDR2/DDR3 General Board Layout Guidelines
      2. 8.7.2 DDR2 Board Design and Layout Guidelines
        1. 8.7.2.1 Board Designs
        2. 8.7.2.2 DDR2 Interface
          1. 8.7.2.2.1  DDR2 Interface Schematic
          2. 8.7.2.2.2  Compatible JEDEC DDR2 Devices
          3. 8.7.2.2.3  PCB Stackup
          4. 8.7.2.2.4  Placement
          5. 8.7.2.2.5  DDR2 Keepout Region
          6. 8.7.2.2.6  Bulk Bypass Capacitors
          7. 8.7.2.2.7  High-Speed Bypass Capacitors
          8. 8.7.2.2.8  Net Classes
          9. 8.7.2.2.9  DDR2 Signal Termination
          10. 8.7.2.2.10 VREF Routing
        3. 8.7.2.3 DDR2 CK and ADDR_CTRL Routing
      3. 8.7.3 DDR3 Board Design and Layout Guidelines
        1. 8.7.3.1  Board Designs
          1. 8.7.3.1.1 DDR3 versus DDR2
        2. 8.7.3.2  DDR3 EMIFs
        3. 8.7.3.3  DDR3 Device Combinations
        4. 8.7.3.4  DDR3 Interface Schematic
          1. 8.7.3.4.1 32-Bit DDR3 Interface
          2. 8.7.3.4.2 16-Bit DDR3 Interface
        5. 8.7.3.5  Compatible JEDEC DDR3 Devices
        6. 8.7.3.6  PCB Stackup
        7. 8.7.3.7  Placement
        8. 8.7.3.8  DDR3 Keepout Region
        9. 8.7.3.9  Bulk Bypass Capacitors
        10. 8.7.3.10 High-Speed Bypass Capacitors
          1. 8.7.3.10.1 Return Current Bypass Capacitors
        11. 8.7.3.11 Net Classes
        12. 8.7.3.12 DDR3 Signal Termination
        13. 8.7.3.13 VREF_DDR Routing
        14. 8.7.3.14 VTT
        15. 8.7.3.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 8.7.3.15.1 Four DDR3 Devices
            1. 8.7.3.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 8.7.3.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 8.7.3.15.2 Two DDR3 Devices
            1. 8.7.3.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 8.7.3.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 8.7.3.15.3 One DDR3 Device
            1. 8.7.3.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 8.7.3.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 8.7.3.16 Data Topologies and Routing Definition
          1. 8.7.3.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 8.7.3.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 8.7.3.17 Routing Specification
          1. 8.7.3.17.1 CK and ADDR_CTRL Routing Specification
          2. 8.7.3.17.2 DQS and DQ Routing Specification
  9. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature and Orderable Information
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Related Links
    5. 9.5 Community Resources
    6. 9.6 商标
    7. 9.7 静电放电警告
    8. 9.8 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information
  11. 重要声明
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TDA2x ADAS 应用 处理器 23mm 封装（ABC 封装）器件版本 2.0

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 器件概述

1.1 特性

  • 专为 ADAS 应用设计的 架构
  • 支持视频、图像和图形处理
    • 全高清视频（1920 × 1080p，60fps）
    • 多个视频输入和视频输出
  • 双核 Arm®Cortex®-A15 微处理器子系统
  • C66x 浮点 VLIW DSP 多达两个
    • 目标代码与 C67x 和 C64x+ 完全兼容
    • 每周期最多 32 次 16 x 16 位定点乘法
  • 片上 L3 RAM 高达 2.5MB
  • 3 级 (L3) 和 4 级 (L4) 互连
  • 两个 DDR2/DDR3/DDR3L 存储器接口 (EMIF) 模块
    • 最高支持 DDR2-800 和 DDR3-1066
    • 每个 EMIF 支持高达 2GB
  • 双核 Arm®Cortex®-M4 图像处理单元 (IPU)
  • Vision AccelerationPac
    • 多达四个嵌入式视觉引擎 (EVE)
  • IVA-HD 子系统
  • 显示子系统
    • 具有 DMA 引擎和多达 3 条管线的显示控制器
    • HDMI™编码器：兼容 HDMI 1.4a 和 DVI 1.0
  • 2D 图形加速器 (BB2D) 子系统
    • Vivante®GC320 内核
  • 视频处理引擎 (VPE)
  • 双核 PowerVR®SGX544 3D GPU
  • 三个视频输入端口 (VIP) 模块
    • 支持多达 10 个多路复用输入端口
  • 通用存储器控制器 (GPMC)
  • 2 端口千兆以太网 (GMAC)
  • 增强型直接存储器存取 (EDMA) 控制器
  • 双控制器局域网 (DCAN) 模块
    • CAN 2.0B 协议
  • 具有®集成 PHY 的 PCI-Express 3.0 端口
    • 一个与第 2 代兼容的双通道端口
    • 或两个与第 2 代兼容的单通道端口
  • 十六个 32 位通用计时器
  • 32 位 MPU 看门狗计时器
  • 10 个可配置 UART/IrDA/CIR 模块
  • 4 个多通道串行外设接口 (McSPI)
  • 四通道 SPI 接口
  • 5 个内部集成电路 (I2C) 端口
  • SATA 接口
  • 8 个多通道音频串行端口 (McASP) 模块
  • 超高速 USB 3.0 双角色器件
  • 三个高速 USB 2.0 双角色器件
  • 四个多媒体卡/安全数字/安全数字输入输出接口 (MMC®/SD®/SDIO)
  • 多达 247 个通用 I/O (GPIO) 引脚
  • 实时时钟子系统 (RTCSS)
  • 器件安全 特性
    • 硬件加密加速器和 DMA
    • 防火墙
    • JTAG®锁
    • 安全密钥
    • 安全 ROM 和引导
  • 电源、复位和时钟管理 (PRSM)
  • 支持 CTools 技术的片上调试
  • 符合汽车级 AEC-Q100 标准
  • 28nm CMOS 技术
  • 23mm × 23mm、0.8mm 间距、760 引脚 BGA (ABC)

1.2 应用

  • 单声道、立体声或 Tri-Optic 前置摄像头
    • 对象检测
    • 行人检测
    • 交通标志识别
    • 车道检测和偏离警告
    • 自动紧急刹车
    • 自适应巡航控制
    • 前部碰撞警告
    • 远光灯辅助
  • LVDS 或以太网环视
    • 2D 环视
    • 3D 环视
    • 车后物体检测
    • 停车辅助
    • 行人检测
    • 车道跟踪
    • 行车记录
  • 传感器融合 – 视觉、雷达、超声波和激光雷达传感器
    • 物体数据融合
    • 原始数据融合

1.3 说明

TI 的全新 TDA2x 片上系统 (SoC) 是经过高度优化的可扩展系列器件，专为满足领先的高级驾驶员辅助系统 (ADAS) 的要求而设计。TDA2x 系列集最佳性能和低功耗特性于一体， 且其 ADAS 视觉分析处理功能有助于实现更自主的无碰撞驾驶体验，从而使其在汽车领域中的 ADAS 应用中得到了广泛的应用。

TDA2x SoC 通过最全面的 ADAS 应用 （包括前置摄像头、泊车辅助、环视和单一架构上的传感器融合），在汽车领域实现了复杂的嵌入式视觉技术。

TDA2x SoC 采用异构可扩展架构，包含 TI 的定点和浮点 TMS320C66x 数字信号处理器 (DSP) 生成内核、Vision AccelerationPac、 Arm®Cortex®-A15 MPCore™ 和双核 Cortex-M4 处理器。该器件集成了用于在以太网 AVB 网络上解码多视频流的视频加速器，以及用于渲染虚拟视图的图形加速器，因此可实现 3D 视觉体验。此外，TDA2x SoC 还集成了诸多外设，包括 LVDS 环视系统的多摄像头接口（并行和串行）、显示屏、CAN 和千兆位以太网 AVB。

适用于本系列产品的 Vision AccelerationPac 包含多个嵌入式视觉引擎 (EVE)，因此应用处理器不用再执行视觉分析功能，同时还降低了功耗。Vision AccelerationPac 针对视觉处理功能进行了优化，具有用于高效程序执行的 32 位 RISC 内核，以及用于专业视觉处理的矢量协处理器。

此外，TI 为 Arm、DSP 和 EVE 协处理器提供了一系列完整的开发工具，其中包括 C 语言编译器、用于简化编程和调度的 DSP 汇编优化器、可查看源代码执行情况的调试界面等。

TDA2x ADAS 处理器符合 AEC-Q100 标准。

器件信息(1)

器件型号 封装 封装尺寸
TDA2SXABC FCBGA (760) 23.0mm x 23.0mm
TDA2SGABC FCBGA (760) 23.0mm x 23.0mm
TDA2SAABC FCBGA (760) 23.0mm x 23.0mm
TDA2HGABC FCBGA (760) 23.0mm x 23.0mm
TDA2HVABC FCBGA (760) 23.0mm x 23.0mm
TDA2HFABC FCBGA (760) 23.0mm x 23.0mm
TDA2LFABC FCBGA (760) 23.0mm x 23.0mm
(1) 更多信息，请参阅，机械、封装和可订购信息。

1.4 功能方框图

Figure 1-1 是该超集的功能框图。

TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF func_sprs859-001.gifFigure 1-1 TDA2x 方框图
  1. ECC 只在 EMIF1 中可用。

2 修订历史记录

Changes from November 30, 2018 to May 15, 2019 (from E Revision (November 2018) to F Revision)

  • Added BB2D and GPU to TDA2HF in Table 3-1, Device ComparisonGo
  • Fixed type direction to “O” for mii1_txer and mii0_txer signals in Table 4-19, GMAC Signal DescriptionsGo
  • Added clarification notes for EMU[1:0] connections in Table 4-21, GPIOs Signal Descriptions and Table 4-30, Debug Signal DescriptionsGo
  • Added MII_TXER timing to GMAC MII Timings sectionGo
  • Updated MDIO Timing Diagram and MDIO7 parameter valuesGo
  • Added note regarding DDR ECC solutions to Table 8-43, Supported DDR3 Device CombinationsGo
  • Added clarifications about validated DDR topology in Section 8.7.3.15, CK and ADDR_CTRL Topologies and Routing DefinitionGo
  • Updated a note for cosmetic marks on the packageGo

3 Device Comparison

Table 3-1 shows a comparison between devices, highlighting the differences.

Table 3-1 Device Comparison(3)

FEATURES DEVICE
TDA2Sxx TDA2Hxx TDA2LFx
TDA2SXx TDA2SGx TDA2SAx TDA2HGx TDA2HVx TDA2HFx
Features
CTRL_WKUP_STD_FUSE_DIE_ID_2[31:24] Base PN register bitfield value (2)(3) 51 (0x33) 50 (0x32) 45 (0x2D) 42 (0x2A) 38 (0x26) 41 (0x29) 25 (0x19)
Processors/Accelerators
Speed Grades T R R R, D T T, F
Dual Arm Cortex-A15 Microprocessor Subsystem (MPU) MPU core 0 Yes Yes Yes Yes Yes
MPU core 1 Yes No No No Yes Yes
C66x VLIW DSP DSP1 Yes Yes Yes Yes No
DSP2 Yes Yes Yes Yes No
BitBLT 2D Hardware Acceleration Engine (BB2D) BB2D Yes No Yes No Yes No
Display Subsystem VOUT1 Yes Yes Yes Yes No
VOUT2 Yes Yes Yes Yes No
VOUT3 Yes Yes Yes Yes No
HDMI Yes Yes Yes Yes No
Embedded Vision Engine (EVE) EVE1 Yes Yes Yes Yes No
EVE2 Yes Yes Yes Yes No
EVE3 Yes Yes No No No
EVE4 Yes Yes No No No
Dual Arm Cortex-M4 Image Processing Unit (IPU) IPU1 Yes Yes Yes Yes Yes
IPU2 Yes Yes Yes Yes Yes
Image Video Accelerator IVA Yes Yes Yes Yes Yes No
SGX544 Dual-Core 3D Graphics Processing Unit GPU Yes No Yes No Yes No
Video Input Port (VIP) VIP1 vin1a Yes Yes Yes Yes No
vin1b Yes Yes Yes Yes No
vin2a Yes Yes Yes Yes No
vin2b Yes Yes Yes Yes No
VIP2 vin3a Yes Yes Yes Yes No
vin3b Yes Yes Yes Yes No
vin4a Yes Yes Yes Yes No
vin4b Yes Yes Yes Yes No
VIP3 vin5a Yes Yes Yes Yes No
vin6a Yes Yes Yes Yes No
Video Processing Engine VPE Yes Yes Yes Yes No
Program/Data Storage
On-Chip Shared Memory (RAM) OCMC_RAM1 512KB 512KB 512KB 512KB 512KB
OCMC_RAM2 1MB 1MB 1MB 1MB 1MB
OCMC_RAM3 1MB 1MB 1MB 1MB 1MB
General-Purpose Memory Controller GPMC Yes Yes Yes Yes Yes
DDR2/DDR3 Memory Controller (1) EMIF1 (with SECDEC) up to 2GB up to 2GB up to 2GB up to 2GB up to 2GB
EMIF2 up to 2GB up to 2GB up to 2GB up to 2GB up to 2GB
Dynamic Memory Manager DMM Yes Yes Yes Yes Yes
Peripherals
Dual Controller Area Network Interface (DCAN) DCAN1 Yes Yes Yes Yes Yes
DCAN2 Yes Yes Yes Yes Yes
Enhanced DMA (EDMA) EDMA Yes Yes Yes Yes Yes
System DMA SDMA Yes Yes Yes Yes Yes
Ethernet Subsystem (Ethernet SS) GMAC_SW[0] Yes Yes Yes Yes Yes
GMAC_SW[1] Yes Yes Yes Yes Yes
Ethernet switch Yes Yes Yes Yes Yes
General-Purpose I/O GPIO up to 247 up to 247 up to 247 up to 247 up to 247
Inter-Integrated Circuit Interface I2C 5 5 5 5 5
System Mailbox Module MAILBOX 13 13 13 13 13
Multichannel Audio Serial Port (McASP) McASP1 16 serializers 16 serializers 16 serializers 16 serializers 16 serializers
McASP2 16 serializers 16 serializers 16 serializers 16 serializers 16 serializers
McASP3 4 serializers 4 serializers 4 serializers 4 serializers 4 serializers
McASP4 4 serializers 4 serializers 4 serializers 4 serializers 4 serializers
McASP5 4 serializers 4 serializers 4 serializers 4 serializers 4 serializers
McASP6 4 serializers 4 serializers 4 serializers 4 serializers 4 serializers
McASP7 4 serializers 4 serializers 4 serializers 4 serializers 4 serializers
McASP8 4 serializers 4 serializers 4 serializers 4 serializers 4 serializers
MultiMedia Card/Secure Digital/Secure Digital Input Output Interface (MMC/SD/SDIO) MMC1 1x UHSI 4b 1x UHSI 4b 1x UHSI 4b 1x UHSI 4b 1x UHSI 4b
MMC2 1x eMMC™ 8b 1x eMMC™ 8b 1x eMMC 8b 1x eMMC 8b 1x eMMC 8b
MMC3 1x SDIO 8b 1x SDIO 8b 1x SDIO 8b 1x SDIO 8b 1x SDIO 8b
MMC4 1x SDIO 4b 1x SDIO 4b 1x SDIO 4b 1x SDIO 4b 1x SDIO 4b
PCI Express 3.0 Port with Integrated PHY PCIe_SS1 Yes Yes Yes Yes Yes
PCIe_SS2 Yes Yes Yes Yes Yes
SATA Gen2 Interface SATA Yes Yes Yes Yes Yes
Real-Time Clock Subsystem RTCSS Yes Yes Yes Yes Yes
Multichannel Serial Peripheral Interface McSPI 4 4 4 4 4
Quad SPI QSPI Yes Yes Yes Yes Yes
Spinlock Module SPINLOCK Yes Yes Yes Yes Yes
Timers, General-Purpose TIMER 16 16 16 16 16
Timer, Watchdog WATCHDOG TIMER Yes Yes Yes Yes Yes
Pulse-Width Modulation Subsystem (PWMSS) PWMSS1 Yes Yes Yes Yes Yes
PWMSS2 Yes Yes Yes Yes Yes
PWMSS3 Yes Yes Yes Yes Yes
Universal Asynchronous Receiver/Transmitter UART 10 10 10 10 10
Universal Serial Bus (USB3.0) USB1 (SuperSpeed, Dual-Role-Device [DRD]) Yes Yes Yes Yes Yes
Universal Serial Bus (USB2.0) USB2 (HighSpeed, Dual-Role-Device [DRD], with embedded HS PHY Yes Yes Yes Yes Yes
USB3 (HighSpeed, OTG2.0, with ULPI) Yes Yes Yes Yes Yes
USB4 (HighSpeed, OTG2.0, with ULPI) Yes Yes Yes Yes Yes
  1. In the Unified L3 memory map, there is maximum of 2GB of SDRAM space which is available to all L3 initiators including MPU (MPU, GPU, DSP, IVA, DMA, etc). Typically this space is interleaved across both EMIFs to optimize memory performance. If a system populates > 2GB of physical memory, that additional addressable space can be accessed only by the MPU via the Arm V7 Large Physical Address Extensions (LPAE).
  2. For more details about the CTRL_WKUP_STD_FUSE_DIE_ID_2 register and Base PN bitfield, see the TDA2x SoC for Advanced Driver Assistance Systems (ADAS) Silicon Revision 2.0, 1.x.
  3. X5777x is the base part number for the superset device. Software should constrain the features used to match the intended production device. The Base PN register bitfield value is 0x3F.

3.1 Related Products

    Automotive Processors
    TDAx ADAS SoCsTI's TDAx Driver Assistance System-on-Chip (SoC) family offers scalable and open solutions and a common hardware and software architecture for Advanced Driver Assistance Systems (ADAS) applications including camera-based front (mono and stereo), rear, surround view and night vision systems, and mid- and long-range radar and sensor fusion systems.
    Companion Products for TDA2Review products that are frequently purchased or used in conjunction with this product.

4 Terminal Configuration and Functions

4.1 Terminal Assignment

Figure 4-1 shows the ball locations for the 760-ball plastic ball grid array (PBGA) package and are used in conjunction with Table 4-2 through Table 4-29 to locate signal names and ball grid numbers.

TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF BALL_ADAS_ABC_001.gifFigure 4-1 ABC S-PBGA-N760 Package (Bottom View)

NOTE

The following balls are not connected: AF7 / AF10 / AF13 / AF16 / AF19 / AE4 / AE25 / AB26 / W3 / W26 / T3 / T26 / N3 / N26 / K3 / K26 / G3 / D4 / D25 / C10 / C13 / C16 / C19 / C22.

These balls do not exist on the package.

4.1.1 Unused Balls Connection Requirements

This section describes the Unused/Reserved balls connection requirements.

NOTE

The following balls are reserved: A27 / K14 / Y5 / Y10 / AA1 / AA2 / AB1 / AB2 / AC1 / AC2 / B28

These balls must be left unconnected.

NOTE

All unused power supply balls must be supplied with the voltages specified in the Section 5.4, Recommended Operating Conditions, unless alternative tie-off options are included in Section 4.4, Signal Descriptions.

Table 4-1 Unused Balls Specific Connection Requirements

BALLS CONNECTION REQUIREMENTS
AE15 / AC15 / AE14 / D20 / AD17 / AC17 / AC16 / AB16 / V27 / AH25 / AE27 / AD27 / Y28 / G28 / H27 / K27 / M28 These balls must be connected to GND through an external pull resistor if unused
V28 / F18 / E20 / E23 / D21 / C20 / C21 / AG25 / AE28 / AD28 / Y27 / G27 / H28 / K28 / M27 / F17 / C25 These balls must be connected to the corresponding power supply through an external pull resistor if unused
AF14 (rtc_iso) This ball should be connected to the corresponding power supply through an external pull resistor if unused; or can be connected to F22 (porz) when RTC unused (level translation may be needed)
AB17 (rtc_porz) This ball should be connected to VSS when RTC is unused; or can be connected to F22 (porz) when RTC unused (level translation may be needed)

NOTE

All other unused signal balls with a Pad Configuration Register can be left unconnected with their internal pullup or pulldown resistor enabled.

NOTE

All other unused signal balls without Pad Configuration Register can be left unconnected.

4.2 Ball Characteristics

Table 4-2 describes the terminal characteristics and the signals multiplexed on each ball. The following list describes the table column headers:

  1. BALL NUMBER: Ball number(s) on the bottom side associated with each signal on the bottom.
  2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).
  3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).

    4. NOTE

    Table 4-2 does not take into account the subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 4.4, Signal Descriptions.

    NOTE

    In the Driver off mode, the buffer is configured in high-impedance.

  4. Hxx/LFx: This column shows if the functionality is applicable for TDA2Hxx / TDA2LFx devices. Note that the ball characteristics table presents the functionality of TDA2Sxx device.
    Hxx - TDA2HGx; TDA2HVx; TDA2HFx;
    LFx - TDA2LFx
  5. MUXMODE: Multiplexing mode number:
    1. MUXMODE 0 is the primary mode; this means that when MUXMODE=0, the function mapped on the pin corresponds to the name of the pin. The primary muxmode is not necessarily the default muxmode.

      2. NOTE

      The default muxmode is the mode at the release of the reset; also see the RESET REL. MUXMODE column.
    2. MUXMODE 1 through 15 are possible muxmodes for alternate functions. On each pin, some muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only MUXMODE values which correspond to defined functions should be used.
    3. An empty box means Not Applicable.
  6. TYPE: Signal type and direction:
    • I = Input
    • O = Output
    • IO = Input or Output
    • D = Open drain
    • DS = Differential Signaling
    • A = Analog
    • PWR = Power
    • GND = Ground
    • CAP = LDO Capacitor
  7. BALL RESET STATE: The state of the terminal at power-on reset:
    • drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated)
    • drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated)
    • OFF: High-impedance
    • PD: High-impedance with an active pulldown resistor
    • PU: High-impedance with an active pullup resistor
    • An empty box means Not Applicable
  8. BALL RESET REL. STATE: The state of the terminal at the deactivation of the rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal)
    • drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated)
    • drive clk (OFF): The buffer drives a toggling clock (pulldown or pullup resistor not activated)
    • drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated)
    • OFF: High-impedance
    • PD: High-impedance with an active pulldown resistor
    • PU: High-impedance with an active pullup resistor
    • An empty box means Not Applicable

    9. NOTE

    For more information on the CORE_PWRON_RET_RST reset signal and its reset sources, see the Power Reset and Clock Management / PRCM Reset Management Functional Description section of the Device TRM.
  9. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal).
    An empty box means Not Applicable.
  10. IO VOLTAGE VALUE: This column describes the IO voltage value (VDDS supply).
    An empty box means Not Applicable.
  11. POWER: The voltage supply that powers the terminal IO buffers.
    An empty box means Not Applicable.
  12. HYS: Indicates if the input buffer is with hysteresis:
    • Yes: With hysteresis
    • No: Without hysteresis
    • An empty box: Not Applicable

    13. NOTE

    For more information, see the hysteresis values in Section 5.7, Electrical Characteristics.
  13. BUFFER TYPE: Drive strength of the associated output buffer.
    An empty box means Not Applicable.

    14. NOTE

    For programmable buffer strength:

    • The default value is given in Table 4-2.
    • A note describes all possible values according to the selected muxmode.
  14. PULLUP / PULLDOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.
    • PU: Internal pullup
    • PD: Internal pulldown
    • PU/PD: Internal pullup and pulldown
    • PUx/PDy: Programmable internal pullup and pulldown
    • PDy: Programmable internal pulldown
    • An empty box means No pull
  15. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0" or logic "1") when the peripheral pin function is not selected by any of the PINCNTLx registers.
    • 0: Logic 0 driven on the peripheral's input signal port.
    • 1: Logic 1 driven on the peripheral's input signal port.
    • blank: Pin state driven on the peripheral's input signal port.

    16. NOTE

    Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration (Hi-Z mode is not an input signal).

    NOTE

    When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be avoided.

    CAUTION

    Peripherals exposed in Ball Characteristics Table and Multiplexing Characteristics Table represent functionality of a superset device. Not all exposed peripherals are supported on ADAS devices. For peripherals supported on ADAS family of products please refer to Table 3-1, Device Comparison.

    NOTE

    Some of the DDR1 and DDR2 signals have an additional state change at the release of porz. The state that the signals change to at the release of porz is as follows:

    drive 0 (OFF) for: ddr1_csn0, ddr1_ck, ddr1_nck, ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_ba[2:0], ddr1_a[15:0], ddr2_csn0, ddr2_ck, ddr2_nck, ddr2_casn, ddr2_rasn, ddr2_wen, ddr2_ba[2:0], ddr2_a[15:0].

    OFF for: ddr1_ecc_d[7:0], ddr1_dqm[3:0], ddr1_dqm_ecc, ddr1_dqs[3:0], ddr1_dqsn[3:0], ddr1_dqs_ecc, ddr1_dqsn_ecc, ddr1_d[31:0], ddr2_dqm[3:0], ddr2_dqs[3:0], ddr2_dqsn[3:0], ddr2_d[31:0].

Table 4-2 Ball Characteristics(1)

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] Hxx/LFx [4] MUXMODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET REL. MUXMODE [9] I/O VOLTAGE VALUE [10] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15]
K9 cap_vbbldo_dspeve cap_vbbldo_dspeve CAP
Y14 cap_vbbldo_gpu cap_vbbldo_gpu CAP
R20 cap_vbbldo_iva cap_vbbldo_iva CAP
J16 cap_vbbldo_mpu cap_vbbldo_mpu CAP
L9 cap_vddram_core1 cap_vddram_core1 CAP
J19 cap_vddram_core2 cap_vddram_core2 CAP
Y15 cap_vddram_core3 cap_vddram_core3 CAP
P19 cap_vddram_core4 cap_vddram_core4 CAP
Y16 cap_vddram_core5 cap_vddram_core5 CAP
J10 cap_vddram_dspeve1 cap_vddram_dspeve1 CAP
J9 cap_vddram_dspeve2 cap_vddram_dspeve2 CAP
Y13 cap_vddram_gpu cap_vddram_gpu CAP
T20 cap_vddram_iva cap_vddram_iva CAP
K16 cap_vddram_mpu1 cap_vddram_mpu1 CAP
K19 cap_vddram_mpu2 cap_vddram_mpu2 CAP
G19 dcan1_rx dcan1_rx 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 1
uart8_txd 2 O
mmc2_sdwp 3 I 0
sata1_led 4 O
hdmi1_cec Yes / No 6 IO
gpio1_15 14 IO
Driver off 15 I
G20 dcan1_tx dcan1_tx 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 1
uart8_rxd 2 I 1
mmc2_sdcd 3 I 1
hdmi1_hpd Yes / No 6 I
gpio1_14 14 IO
Driver off 15 I
AD20 ddr1_a0 ddr1_a0 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AC19 ddr1_a1 ddr1_a1 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AC20 ddr1_a2 ddr1_a2 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AB19 ddr1_a3 ddr1_a3 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AF21 ddr1_a4 ddr1_a4 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AH22 ddr1_a5 ddr1_a5 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AG23 ddr1_a6 ddr1_a6 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AE21 ddr1_a7 ddr1_a7 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AF22 ddr1_a8 ddr1_a8 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AE22 ddr1_a9 ddr1_a9 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AD21 ddr1_a10 ddr1_a10 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AD22 ddr1_a11 ddr1_a11 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AC21 ddr1_a12 ddr1_a12 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AF18 ddr1_a13 ddr1_a13 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AE17 ddr1_a14 ddr1_a14 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AD18 ddr1_a15 ddr1_a15 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AF17 ddr1_ba0 ddr1_ba0 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AE18 ddr1_ba1 ddr1_ba1 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AB18 ddr1_ba2 ddr1_ba2 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AC18 ddr1_casn ddr1_casn 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AG24 ddr1_ck ddr1_ck 0 O PD drive clk (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AG22 ddr1_cke ddr1_cke 0 O PD drive 0 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AH23 ddr1_csn0 ddr1_csn0 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AF25 ddr1_d0 ddr1_d0 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AF26 ddr1_d1 ddr1_d1 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AG26 ddr1_d2 ddr1_d2 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AH26 ddr1_d3 ddr1_d3 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AF24 ddr1_d4 ddr1_d4 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AE24 ddr1_d5 ddr1_d5 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AF23 ddr1_d6 ddr1_d6 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AE23 ddr1_d7 ddr1_d7 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AC23 ddr1_d8 ddr1_d8 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AF27 ddr1_d9 ddr1_d9 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AG27 ddr1_d10 ddr1_d10 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AF28 ddr1_d11 ddr1_d11 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AE26 ddr1_d12 ddr1_d12 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AC25 ddr1_d13 ddr1_d13 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AC24 ddr1_d14 ddr1_d14 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AD25 ddr1_d15 ddr1_d15 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
V20 ddr1_d16 ddr1_d16 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
W20 ddr1_d17 ddr1_d17 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AB28 ddr1_d18 ddr1_d18 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AC28 ddr1_d19 ddr1_d19 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AC27 ddr1_d20 ddr1_d20 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
Y19 ddr1_d21 ddr1_d21 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AB27 ddr1_d22 ddr1_d22 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
Y20 ddr1_d23 ddr1_d23 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AA23 ddr1_d24 ddr1_d24 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
Y22 ddr1_d25 ddr1_d25 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
Y23 ddr1_d26 ddr1_d26 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AA24 ddr1_d27 ddr1_d27 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
Y24 ddr1_d28 ddr1_d28 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AA26 ddr1_d29 ddr1_d29 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AA25 ddr1_d30 ddr1_d30 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AA28 ddr1_d31 ddr1_d31 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AD23 ddr1_dqm0 ddr1_dqm0 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AB23 ddr1_dqm1 ddr1_dqm1 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AC26 ddr1_dqm2 ddr1_dqm2 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AA27 ddr1_dqm3 ddr1_dqm3 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
V26 ddr1_dqm_ecc ddr1_dqm_ecc 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AH25 ddr1_dqs0 ddr1_dqs0 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR Pux/PDy
AE27 ddr1_dqs1 ddr1_dqs1 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR Pux/PDy
AD27 ddr1_dqs2 ddr1_dqs2 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR Pux/PDy
Y28 ddr1_dqs3 ddr1_dqs3 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR Pux/PDy
AG25 ddr1_dqsn0 ddr1_dqsn0 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR Pux/PDy
AE28 ddr1_dqsn1 ddr1_dqsn1 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR Pux/PDy
AD28 ddr1_dqsn2 ddr1_dqsn2 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR Pux/PDy
Y27 ddr1_dqsn3 ddr1_dqsn3 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR Pux/PDy
V28 ddr1_dqsn_ecc ddr1_dqsn_ecc 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR Pux/PDy
V27 ddr1_dqs_ecc ddr1_dqs_ecc 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR Pux/PDy
W22 ddr1_ecc_d0 ddr1_ecc_d0 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
V23 ddr1_ecc_d1 ddr1_ecc_d1 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
W19 ddr1_ecc_d2 ddr1_ecc_d2 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
W23 ddr1_ecc_d3 ddr1_ecc_d3 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
Y25 ddr1_ecc_d4 ddr1_ecc_d4 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
V24 ddr1_ecc_d5 ddr1_ecc_d5 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
V25 ddr1_ecc_d6 ddr1_ecc_d6 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
Y26 ddr1_ecc_d7 ddr1_ecc_d7 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AH24 ddr1_nck ddr1_nck 0 O PD drive clk (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AE20 ddr1_odt0 ddr1_odt0 0 O PD drive 0 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AF20 ddr1_rasn ddr1_rasn 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
AG21 ddr1_rst ddr1_rst 0 O PD drive 0 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
Y18 ddr1_vref0 ddr1_vref0 0 PWR OFF OFF 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR
AH21 ddr1_wen ddr1_wen 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy
R25 ddr2_a0 ddr2_a0 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
R26 ddr2_a1 ddr2_a1 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
R28 ddr2_a2 ddr2_a2 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
R27 ddr2_a3 ddr2_a3 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
P23 ddr2_a4 ddr2_a4 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
P22 ddr2_a5 ddr2_a5 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
P25 ddr2_a6 ddr2_a6 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
N20 ddr2_a7 ddr2_a7 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
P27 ddr2_a8 ddr2_a8 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
N27 ddr2_a9 ddr2_a9 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
N23 ddr2_a10 ddr2_a10 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
P26 ddr2_a11 ddr2_a11 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
N28 ddr2_a12 ddr2_a12 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
T22 ddr2_a13 ddr2_a13 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
R22 ddr2_a14 ddr2_a14 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
U22 ddr2_a15 ddr2_a15 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
U23 ddr2_ba0 ddr2_ba0 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
U27 ddr2_ba1 ddr2_ba1 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
U26 ddr2_ba2 ddr2_ba2 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
U28 ddr2_casn ddr2_casn 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
T28 ddr2_ck ddr2_ck 0 O PD drive clk (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
U24 ddr2_cke ddr2_cke 0 O PD drive 0 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
P24 ddr2_csn0 ddr2_csn0 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
E26 ddr2_d0 ddr2_d0 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
G25 ddr2_d1 ddr2_d1 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
F25 ddr2_d2 ddr2_d2 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
F24 ddr2_d3 ddr2_d3 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
F26 ddr2_d4 ddr2_d4 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
F27 ddr2_d5 ddr2_d5 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
E27 ddr2_d6 ddr2_d6 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
E28 ddr2_d7 ddr2_d7 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
H23 ddr2_d8 ddr2_d8 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
H25 ddr2_d9 ddr2_d9 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
H24 ddr2_d10 ddr2_d10 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
H26 ddr2_d11 ddr2_d11 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
G26 ddr2_d12 ddr2_d12 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
J25 ddr2_d13 ddr2_d13 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
J26 ddr2_d14 ddr2_d14 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
J24 ddr2_d15 ddr2_d15 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
L22 ddr2_d16 ddr2_d16 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
K20 ddr2_d17 ddr2_d17 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
K21 ddr2_d18 ddr2_d18 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
L23 ddr2_d19 ddr2_d19 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
L24 ddr2_d20 ddr2_d20 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
J23 ddr2_d21 ddr2_d21 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
K22 ddr2_d22 ddr2_d22 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
J20 ddr2_d23 ddr2_d23 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
L27 ddr2_d24 ddr2_d24 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
L26 ddr2_d25 ddr2_d25 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
L25 ddr2_d26 ddr2_d26 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
L28 ddr2_d27 ddr2_d27 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
M23 ddr2_d28 ddr2_d28 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
M24 ddr2_d29 ddr2_d29 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
M25 ddr2_d30 ddr2_d30 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
M26 ddr2_d31 ddr2_d31 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
F28 ddr2_dqm0 ddr2_dqm0 0 O PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
G24 ddr2_dqm1 ddr2_dqm1 0 O PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
K23 ddr2_dqm2 ddr2_dqm2 0 O PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
M22 ddr2_dqm3 ddr2_dqm3 0 O PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
G28 ddr2_dqs0 ddr2_dqs0 0 IO PD PD 1.35/1.5/1.8 vdds_ddr2 LVCMOS DDR Pux/PDy
H27 ddr2_dqs1 ddr2_dqs1 0 IO PD PD 1.35/1.5/1.8 vdds_ddr2 LVCMOS DDR Pux/PDy
K27 ddr2_dqs2 ddr2_dqs2 0 IO PD PD 1.35/1.5/1.8 vdds_ddr2 LVCMOS DDR Pux/PDy
M28 ddr2_dqs3 ddr2_dqs3 0 IO PD PD 1.35/1.5/1.8 vdds_ddr2 LVCMOS DDR Pux/PDy
G27 ddr2_dqsn0 ddr2_dqsn0 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 LVCMOS DDR Pux/PDy
H28 ddr2_dqsn1 ddr2_dqsn1 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 LVCMOS DDR Pux/PDy
K28 ddr2_dqsn2 ddr2_dqsn2 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 LVCMOS DDR Pux/PDy
M27 ddr2_dqsn3 ddr2_dqsn3 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 LVCMOS DDR Pux/PDy
T27 ddr2_nck ddr2_nck 0 O PD drive clk (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
R23 ddr2_odt0 ddr2_odt0 0 O PD drive 0 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
T23 ddr2_rasn ddr2_rasn 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
R24 ddr2_rst ddr2_rst 0 O PD drive 0 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
N22 ddr2_vref0 ddr2_vref0 0 PWR OFF OFF 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR
U25 ddr2_wen ddr2_wen 0 O PD drive 1 (OFF) 1.35/1.5/1.8 vdds_ddr2 No LVCMOS DDR Pux/PDy
G21 emu0 emu0 0 IO PU PU 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio8_30 14 IO
D24 emu1 emu1 0 IO PU PU 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio8_31 14 IO
AC5 gpio6_10 gpio6_10 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
mdio_mclk 1 O 1
i2c3_sda 2 IO 1
usb3_ulpi_d7 3 IO 0
vin2b_hsync1 Yes / No 4 I
vin5a_clk0 Yes / No 9 I 0
ehrpwm2A 10 O
gpio6_10 14 IO
Driver off 15 I
AB4 gpio6_11 gpio6_11 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
mdio_d 1 IO 1
i2c3_scl 2 IO 1
usb3_ulpi_d6 3 IO 0
vin2b_vsync1 Yes / No 4 I
vin5a_de0 Yes / No 9 I 0
ehrpwm2B 10 O
gpio6_11 14 IO
Driver off 15 I
E21 gpio6_14 gpio6_14 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr8 1 IO 0
dcan2_tx 2 IO 1
uart10_rxd 3 I 1
vout2_hsync Yes / No 6 O
vin4a_hsync0 Yes / No 8 I 0
i2c3_sda 9 IO 1
timer1 10 IO
gpio6_14 14 IO
Driver off 15 I
F20 gpio6_15 gpio6_15 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr9 1 IO 0
dcan2_rx 2 IO 1
uart10_txd 3 O
vout2_vsync Yes / No 6 O
vin4a_vsync0 Yes / No 8 I 0
i2c3_scl 9 IO 1
timer2 10 IO
gpio6_15 14 IO
Driver off 15 I
F21 gpio6_16 gpio6_16 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr10 1 IO 0
vout2_fld Yes / No 6 O
vin4a_fld0 Yes / No 8 I 0
clkout1 9 O
timer3 10 IO
gpio6_16 14 IO
Driver off 15 I
R6 gpmc_a0 gpmc_a0 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin3a_d16 Yes / No 2 I 0
vout3_d16 Yes / No 3 O
vin4a_d0 Yes / No 4 I 0
vin4b_d0 Yes / No 6 I 0
i2c4_scl 7 IO 1
uart5_rxd 8 I 1
gpio7_3 14 IO
Driver off 15 I
T9 gpmc_a1 gpmc_a1 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin3a_d17 Yes / No 2 I 0
vout3_d17 Yes / No 3 O
vin4a_d1 Yes / No 4 I 0
vin4b_d1 Yes / No 6 I 0
i2c4_sda 7 IO 1
uart5_txd 8 O
gpio7_4 14 IO
Driver off 15 I
T6 gpmc_a2 gpmc_a2 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin3a_d18 Yes / No 2 I 0
vout3_d18 Yes / No 3 O
vin4a_d2 Yes / No 4 I 0
vin4b_d2 Yes / No 6 I 0
uart7_rxd 7 I 1
uart5_ctsn 8 I 1
gpio7_5 14 IO
Driver off 15 I
T7 gpmc_a3 gpmc_a3 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_cs2 1 O 1
vin3a_d19 Yes / No 2 I 0
vout3_d19 Yes / No 3 O
vin4a_d3 Yes / No 4 I 0
vin4b_d3 Yes / No 6 I 0
uart7_txd 7 O
uart5_rtsn 8 O
gpio7_6 14 IO
Driver off 15 I
P6 gpmc_a4 gpmc_a4 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_cs3 1 O 1
vin3a_d20 Yes / No 2 I 0
vout3_d20 Yes / No 3 O
vin4a_d4 Yes / No 4 I 0
vin4b_d4 Yes / No 6 I 0
i2c5_scl 7 IO 1
uart6_rxd 8 I 1
gpio1_26 14 IO
Driver off 15 I
R9 gpmc_a5 gpmc_a5 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin3a_d21 Yes / No 2 I 0
vout3_d21 Yes / No 3 O
vin4a_d5 Yes / No 4 I 0
vin4b_d5 Yes / No 6 I 0
i2c5_sda 7 IO 1
uart6_txd 8 O
gpio1_27 14 IO
Driver off 15 I
R5 gpmc_a6 gpmc_a6 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin3a_d22 Yes / No 2 I 0
vout3_d22 Yes / No 3 O
vin4a_d6 Yes / No 4 I 0
vin4b_d6 Yes / No 6 I 0
uart8_rxd 7 I 1
uart6_ctsn 8 I 1
gpio1_28 14 IO
Driver off 15 I
P5 gpmc_a7 gpmc_a7 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin3a_d23 Yes / No 2 I 0
vout3_d23 Yes / No 3 O
vin4a_d7 Yes / No 4 I 0
vin4b_d7 Yes / No 6 I 0
uart8_txd 7 O
uart6_rtsn 8 O
gpio1_29 14 IO
Driver off 15 I
N7 gpmc_a8 gpmc_a8 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin3a_hsync0 Yes / No 2 I 0
vout3_hsync Yes / No 3 O
vin4b_hsync1 Yes / No 6 I 0
timer12 7 IO
spi4_sclk 8 IO 0
gpio1_30 14 IO
Driver off 15 I
R4 gpmc_a9 gpmc_a9 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin3a_vsync0 Yes / No 2 I 0
vout3_vsync Yes / No 3 O
vin4b_vsync1 Yes / No 6 I 0
timer11 7 IO
spi4_d1 8 IO 0
gpio1_31 14 IO
Driver off 15 I
N9 gpmc_a10 gpmc_a10 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin3a_de0 Yes / No 2 I 0
vout3_de Yes / No 3 O
vin4b_clk1 Yes / No 6 I 0
timer10 7 IO
spi4_d0 8 IO 0
gpio2_0 14 IO
Driver off 15 I
P9 gpmc_a11 gpmc_a11 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin3a_fld0 Yes / No 2 I 0
vout3_fld Yes / No 3 O
vin4a_fld0 Yes / No 4 I 0
vin4b_de1 Yes / No 6 I 0
timer9 7 IO
spi4_cs0 8 IO 1
gpio2_1 14 IO
Driver off 15 I
P4 gpmc_a12 gpmc_a12 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin4a_clk0 Yes / No 4 I 0
gpmc_a0 5 O
vin4b_fld1 Yes / No 6 I 0
timer8 7 IO
spi4_cs1 8 IO 1
dma_evt1 9 I 0
gpio2_2 14 IO
Driver off 15 I
R3 gpmc_a13 gpmc_a13 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_rtclk 1 I 0
vin4a_hsync0 Yes / No 4 I 0
timer7 7 IO
spi4_cs2 8 IO 1
dma_evt2 9 I 0
gpio2_3 14 IO
Driver off 15 I
T2 gpmc_a14 gpmc_a14 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_d3 1 I 0
vin4a_vsync0 Yes / No 4 I 0
timer6 7 IO
spi4_cs3 8 IO 1
gpio2_4 14 IO
Driver off 15 I
U2 gpmc_a15 gpmc_a15 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_d2 1 I 0
vin4a_d8 Yes / No 4 I 0
timer5 7 IO
gpio2_5 14 IO
Driver off 15 I
U1 gpmc_a16 gpmc_a16 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_d0 1 IO 0
vin4a_d9 Yes / No 4 I 0
gpio2_6 14 IO
Driver off 15 I
P3 gpmc_a17 gpmc_a17 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_d1 1 I 0
vin4a_d10 Yes / No 4 I 0
gpio2_7 14 IO
Driver off 15 I
R2 gpmc_a18 gpmc_a18 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_sclk 1 O
vin4a_d11 Yes / No 4 I 0
gpio2_8 14 IO
Driver off 15 I
K7 (9) gpmc_a19 gpmc_a19 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat4 1 IO 1
gpmc_a13 2 O
vin4a_d12 Yes / No 4 I 0
vin3b_d0 Yes / No 6 I 0
gpio2_9 14 IO
Driver off 15 I
M7 (9) gpmc_a20 gpmc_a20 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat5 1 IO 1
gpmc_a14 2 O
vin4a_d13 Yes / No 4 I 0
vin3b_d1 Yes / No 6 I 0
gpio2_10 14 IO
Driver off 15 I
J5 (9) gpmc_a21 gpmc_a21 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat6 1 IO 1
gpmc_a15 2 O
vin4a_d14 Yes / No 4 I 0
vin3b_d2 Yes / No 6 I 0
gpio2_11 14 IO
Driver off 15 I
K6 (9) gpmc_a22 gpmc_a22 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat7 1 IO 1
gpmc_a16 2 O
vin4a_d15 Yes / No 4 I 0
vin3b_d3 Yes / No 6 I 0
gpio2_12 14 IO
Driver off 15 I
J7 gpmc_a23 gpmc_a23 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_clk 1 IO 1
gpmc_a17 2 O
vin4a_fld0 Yes / No 4 I 0
vin3b_d4 Yes / No 6 I 0
gpio2_13 14 IO
Driver off 15 I
J4 (9) gpmc_a24 gpmc_a24 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat0 1 IO 1
gpmc_a18 2 O
vin3b_d5 Yes / No 6 I 0
gpio2_14 14 IO
Driver off 15 I
J6 (9) gpmc_a25 gpmc_a25 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat1 1 IO 1
gpmc_a19 2 O
vin3b_d6 Yes / No 6 I 0
gpio2_15 14 IO
Driver off 15 I
H4 (9) gpmc_a26 gpmc_a26 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat2 1 IO 1
gpmc_a20 2 O
vin3b_d7 Yes / No 6 I 0
gpio2_16 14 IO
Driver off 15 I
H5 (9) gpmc_a27 gpmc_a27 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat3 1 IO 1
gpmc_a21 2 O
vin3b_hsync1 Yes / No 6 I 0
gpio2_17 14 IO
Driver off 15 I
M6 gpmc_ad0 gpmc_ad0 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin3a_d0 Yes / No 2 I 0
vout3_d0 Yes / No 3 O
gpio1_6 14 IO
sysboot0 15 I
M2 gpmc_ad1 gpmc_ad1 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin3a_d1 Yes / No 2 I 0
vout3_d1 Yes / No 3 O
gpio1_7 14 IO
sysboot1 15 I
L5 gpmc_ad2 gpmc_ad2 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin3a_d2 Yes / No 2 I 0
vout3_d2 Yes / No 3 O
gpio1_8 14 IO
sysboot2 15 I
M1 gpmc_ad3 gpmc_ad3 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin3a_d3 Yes / No 2 I 0
vout3_d3 Yes / No 3 O
gpio1_9 14 IO
sysboot3 15 I
L6 gpmc_ad4 gpmc_ad4 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin3a_d4 Yes / No 2 I 0
vout3_d4 Yes / No 3 O
gpio1_10 14 IO
sysboot4 15 I
L4 gpmc_ad5 gpmc_ad5 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin3a_d5 Yes / No 2 I 0
vout3_d5 Yes / No 3 O
gpio1_11 14 IO
sysboot5 15 I
L3 gpmc_ad6 gpmc_ad6 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin3a_d6 Yes / No 2 I 0
vout3_d6 Yes / No 3 O
gpio1_12 14 IO
sysboot6 15 I
L2 gpmc_ad7 gpmc_ad7 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin3a_d7 Yes / No 2 I 0
vout3_d7 Yes / No 3 O
gpio1_13 14 IO
sysboot7 15 I
L1 gpmc_ad8 gpmc_ad8 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin3a_d8 Yes / No 2 I 0
vout3_d8 Yes / No 3 O
gpio7_18 14 IO
sysboot8 15 I
K2 gpmc_ad9 gpmc_ad9 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin3a_d9 Yes / No 2 I 0
vout3_d9 Yes / No 3 O
gpio7_19 14 IO
sysboot9 15 I
J1 gpmc_ad10 gpmc_ad10 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin3a_d10 Yes / No 2 I 0
vout3_d10 Yes / No 3 O
gpio7_28 14 IO
sysboot10 15 I
J2 gpmc_ad11 gpmc_ad11 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin3a_d11 Yes / No 2 I 0
vout3_d11 Yes / No 3 O
gpio7_29 14 IO
sysboot11 15 I
H1 gpmc_ad12 gpmc_ad12 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin3a_d12 Yes / No 2 I 0
vout3_d12 Yes / No 3 O
gpio1_18 14 IO
sysboot12 15 I
J3 gpmc_ad13 gpmc_ad13 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin3a_d13 Yes / No 2 I 0
vout3_d13 Yes / No 3 O
gpio1_19 14 IO
sysboot13 15 I
H2 gpmc_ad14 gpmc_ad14 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin3a_d14 Yes / No 2 I 0
vout3_d14 Yes / No 3 O
gpio1_20 14 IO
sysboot14 15 I
H3 gpmc_ad15 gpmc_ad15 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin3a_d15 Yes / No 2 I 0
vout3_d15 Yes / No 3 O
gpio1_21 14 IO
sysboot15 15 I
N1 gpmc_advn_ale gpmc_advn_ale 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpmc_cs6 1 O
clkout2 2 O
gpmc_wait1 3 I 1
vin4a_vsync0 Yes / No 4 I 0
gpmc_a2 5 O
gpmc_a23 6 O
timer3 7 IO
i2c3_sda 8 IO 1
dma_evt2 9 I 0
gpio2_23 14 IO
Driver off 15 I
N6 gpmc_ben0 gpmc_ben0 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpmc_cs4 1 O
vin1b_hsync1 Yes / No 3 I 0
vin3b_de1 Yes / No 6 I 0
timer2 7 IO
dma_evt3 9 I 0
gpio2_26 14 IO
Driver off 15 I
M4 gpmc_ben1 gpmc_ben1 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpmc_cs5 1 O
vin1b_de1 Yes / No 3 I 0
vin3b_clk1 Yes / No 4 I 0
gpmc_a3 5 O
vin3b_fld1 Yes / No 6 I 0
timer1 7 IO
dma_evt4 9 I 0
gpio2_27 14 IO
Driver off 15 I
P7 gpmc_clk gpmc_clk 0 IO PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
gpmc_cs7 1 O
clkout1 2 O
gpmc_wait1 3 I 1
vin4a_hsync0 Yes / No 4 I 0
vin4a_de0 Yes / No 5 I 0
vin3b_clk1 Yes / No 6 I 0
timer4 7 IO
i2c3_scl 8 IO 1
dma_evt1 9 I 0
gpio2_22 14 IO
Driver off 15 I
T1 gpmc_cs0 gpmc_cs0 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpio2_19 14 IO
Driver off 15 I
H6 gpmc_cs1 gpmc_cs1 0 O PU PU 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_cmd 1 IO 1
gpmc_a22 2 O
vin4a_de0 Yes / No 4 I 0
vin3b_vsync1 Yes / No 6 I 0
gpio2_18 14 IO
Driver off 15 I
P2 gpmc_cs2 gpmc_cs2 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_cs0 1 O 1
gpio2_20 14 IO
Driver off 15 I
P1 gpmc_cs3 gpmc_cs3 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_cs1 1 O 1
vin3a_clk0 Yes / No 2 I 0
vout3_clk Yes / No 3 O
gpmc_a1 5 O
gpio2_21 14 IO
Driver off 15 I
M5 gpmc_oen_ren gpmc_oen_ren 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpio2_24 14 IO
Driver off 15 I
N2 gpmc_wait0 gpmc_wait0 0 I PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 1
gpio2_28 14 IO
Driver off 15 I
M3 gpmc_wen gpmc_wen 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpio2_25 14 IO
Driver off 15 I
AG16 hdmi1_clockx hdmi1_clockx Yes / No 0 O 1.8 vdda_hdmi HDMIPHY PDy
AH16 hdmi1_clocky hdmi1_clocky Yes / No 0 O 1.8 vdda_hdmi HDMIPHY PDy
AG17 hdmi1_data0x hdmi1_data0x Yes / No 0 O 1.8 vdda_hdmi HDMIPHY PDy
AH17 hdmi1_data0y hdmi1_data0y Yes / No 0 O 1.8 vdda_hdmi HDMIPHY PDy
AG18 hdmi1_data1x hdmi1_data1x Yes / No 0 O 1.8 vdda_hdmi HDMIPHY PDy
AH18 hdmi1_data1y hdmi1_data1y Yes / No 0 O 1.8 vdda_hdmi HDMIPHY PDy
AG19 hdmi1_data2x hdmi1_data2x Yes / No 0 O 1.8 vdda_hdmi HDMIPHY PDy
AH19 hdmi1_data2y hdmi1_data2y Yes / No 0 O 1.8 vdda_hdmi HDMIPHY PDy
C20 i2c1_scl i2c1_scl 0 IO OFF OFF 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS I2C PU/PD
C21 i2c1_sda i2c1_sda 0 IO OFF OFF 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS I2C PU/PD
F17 i2c2_scl i2c2_scl 0 IO OFF OFF 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS I2C PU/PD 1
hdmi1_ddc_sda Yes / No 1 IO
Driver off 15 I
C25 i2c2_sda i2c2_sda 0 IO OFF OFF 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS I2C PU/PD 1
hdmi1_ddc_scl Yes / No 1 IO
Driver off 15 I
AH15 ljcb_clkn ljcb_clkn 0 IO 1.8 vdda_pcie LJCB
AG15 ljcb_clkp ljcb_clkp 0 IO 1.8 vdda_pcie LJCB
B14 mcasp1_aclkr mcasp1_aclkr 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp7_axr2 1 IO 0
vout2_d0 Yes / No 6 O
vin4a_d0 Yes / No 8 I 0
i2c4_sda 10 IO 1
gpio5_0 14 IO
Driver off 15 I
C14 mcasp1_aclkx mcasp1_aclkx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
vin6a_fld0 Yes / No 7 I 0
i2c3_sda 10 IO 1
gpio7_31 14 IO
Driver off 15 I
G12 mcasp1_axr0 mcasp1_axr0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
uart6_rxd 3 I 1
vin6a_vsync0 Yes / No 7 I 0
i2c5_sda 10 IO 1
gpio5_2 14 IO
Driver off 15 I
F12 mcasp1_axr1 mcasp1_axr1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
uart6_txd 3 O
vin6a_hsync0 Yes / No 7 I 0
i2c5_scl 10 IO 1
gpio5_3 14 IO
Driver off 15 I
G13 mcasp1_axr2 mcasp1_axr2 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp6_axr2 1 IO 0
uart6_ctsn 3 I 1
vout2_d2 Yes / No 6 O
vin4a_d2 Yes / No 8 I 0
gpio5_4 14 IO
Driver off 15 I
J11 mcasp1_axr3 mcasp1_axr3 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp6_axr3 1 IO 0
uart6_rtsn 3 O
vout2_d3 Yes / No 6 O
vin4a_d3 Yes / No 8 I 0
gpio5_5 14 IO
Driver off 15 I
E12 mcasp1_axr4 mcasp1_axr4 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp4_axr2 1 IO 0
vout2_d4 Yes / No 6 O
vin4a_d4 Yes / No 8 I 0
gpio5_6 14 IO
Driver off 15 I
F13 mcasp1_axr5 mcasp1_axr5 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp4_axr3 1 IO 0
vout2_d5 Yes / No 6 O
vin4a_d5 Yes / No 8 I 0
gpio5_7 14 IO
Driver off 15 I
C12 mcasp1_axr6 mcasp1_axr6 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp5_axr2 1 IO 0
vout2_d6 Yes / No 6 O
vin4a_d6 Yes / No 8 I 0
gpio5_8 14 IO
Driver off 15 I
D12 mcasp1_axr7 mcasp1_axr7 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp5_axr3 1 IO 0
vout2_d7 Yes / No 6 O
vin4a_d7 Yes / No 8 I 0
timer4 10 IO
gpio5_9 14 IO
Driver off 15 I
B12 mcasp1_axr8 mcasp1_axr8 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp6_axr0 1 IO 0
spi3_sclk 3 IO 0
vin6a_d15 Yes / No 7 I 0
timer5 10 IO
gpio5_10 14 IO
Driver off 15 I
A11 mcasp1_axr9 mcasp1_axr9 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp6_axr1 1 IO 0
spi3_d1 3 IO 0
vin6a_d14 Yes / No 7 I 0
timer6 10 IO
gpio5_11 14 IO
Driver off 15 I
B13 mcasp1_axr10 mcasp1_axr10 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp6_aclkx 1 IO 0
mcasp6_aclkr 2 IO
spi3_d0 3 IO 0
vin6a_d13 Yes / No 7 I 0
timer7 10 IO
gpio5_12 14 IO
Driver off 15 I
A12 mcasp1_axr11 mcasp1_axr11 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp6_fsx 1 IO 0
mcasp6_fsr 2 IO
spi3_cs0 3 IO 1
vin6a_d12 Yes / No 7 I 0
timer8 10 IO
gpio4_17 14 IO
Driver off 15 I
E14 mcasp1_axr12 mcasp1_axr12 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp7_axr0 1 IO 0
spi3_cs1 3 IO 1
vin6a_d11 Yes / No 7 I 0
timer9 10 IO
gpio4_18 14 IO
Driver off 15 I
A13 mcasp1_axr13 mcasp1_axr13 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp7_axr1 1 IO 0
vin6a_d10 Yes / No 7 I 0
timer10 10 IO
gpio6_4 14 IO
Driver off 15 I
G14 mcasp1_axr14 mcasp1_axr14 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp7_aclkx 1 IO 0
mcasp7_aclkr 2 IO
vin6a_d9 Yes / No 7 I 0
timer11 10 IO
gpio6_5 14 IO
Driver off 15 I
F14 mcasp1_axr15 mcasp1_axr15 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp7_fsx 1 IO 0
mcasp7_fsr 2 IO
vin6a_d8 Yes / No 7 I 0
timer12 10 IO
gpio6_6 14 IO
Driver off 15 I
J14 mcasp1_fsr mcasp1_fsr 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp7_axr3 1 IO 0
vout2_d1 Yes / No 6 O
vin4a_d1 Yes / No 8 I 0
i2c4_scl 10 IO 1
gpio5_1 14 IO
Driver off 15 I
D14 mcasp1_fsx mcasp1_fsx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
vin6a_de0 Yes / No 7 I 0
i2c3_scl 10 IO 1
gpio7_30 14 IO
Driver off 15 I
E15 mcasp2_aclkr mcasp2_aclkr 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp8_axr2 1 IO 0
vout2_d8 Yes / No 6 O
vin4a_d8 Yes / No 8 I 0
Driver off 15 I
A19 mcasp2_aclkx mcasp2_aclkx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
vin6a_d7 Yes / No 7 I 0
Driver off 15 I
B15 mcasp2_axr0 mcasp2_axr0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
vout2_d10 Yes / No 6 O
vin4a_d10 Yes / No 8 I 0
Driver off 15 I
A15 mcasp2_axr1 mcasp2_axr1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
vout2_d11 Yes / No 6 O
vin4a_d11 Yes / No 8 I 0
Driver off 15 I
C15 mcasp2_axr2 mcasp2_axr2 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp3_axr2 1 IO 0
vin6a_d5 Yes / No 7 I 0
gpio6_8 14 IO
Driver off 15 I
A16 mcasp2_axr3 mcasp2_axr3 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp3_axr3 1 IO 0
vin6a_d4 Yes / No 7 I 0
gpio6_9 14 IO
Driver off 15 I
D15 mcasp2_axr4 mcasp2_axr4 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp8_axr0 1 IO 0
vout2_d12 Yes / No 6 O
vin4a_d12 Yes / No 8 I 0
gpio1_4 14 IO
Driver off 15 I
B16 mcasp2_axr5 mcasp2_axr5 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp8_axr1 1 IO 0
vout2_d13 Yes / No 6 O
vin4a_d13 Yes / No 8 I 0
gpio6_7 14 IO
Driver off 15 I
B17 mcasp2_axr6 mcasp2_axr6 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp8_aclkx 1 IO 0
mcasp8_aclkr 2 IO
vout2_d14 Yes / No 6 O
vin4a_d14 Yes / No 8 I 0
gpio2_29 14 IO
Driver off 15 I
A17 mcasp2_axr7 mcasp2_axr7 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp8_fsx 1 IO 0
mcasp8_fsr 2 IO
vout2_d15 Yes / No 6 O
vin4a_d15 Yes / No 8 I 0
gpio1_5 14 IO
Driver off 15 I
A20 mcasp2_fsr mcasp2_fsr 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp8_axr3 1 IO 0
vout2_d9 Yes / No 6 O
vin4a_d9 Yes / No 8 I 0
Driver off 15 I
A18 mcasp2_fsx mcasp2_fsx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
vin6a_d6 Yes / No 7 I 0
Driver off 15 I
B18 mcasp3_aclkx mcasp3_aclkx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp3_aclkr 1 IO
mcasp2_axr12 2 IO 0
uart7_rxd 3 I 1
vin6a_d3 Yes / No 7 I 0
gpio5_13 14 IO
Driver off 15 I
B19 mcasp3_axr0 mcasp3_axr0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp2_axr14 2 IO 0
uart7_ctsn 3 I 1
uart5_rxd 4 I 1
vin6a_d1 Yes / No 7 I 0
Driver off 15 I
C17 mcasp3_axr1 mcasp3_axr1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp2_axr15 2 IO 0
uart7_rtsn 3 O
uart5_txd 4 O
vin6a_d0 Yes / No 7 I 0
vin5a_fld0 Yes / No 9 I 0
Driver off 15 I
F15 mcasp3_fsx mcasp3_fsx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp3_fsr 1 IO
mcasp2_axr13 2 IO 0
uart7_txd 3 O
vin6a_d2 Yes / No 7 I 0
gpio5_14 14 IO
Driver off 15 I
C18 mcasp4_aclkx mcasp4_aclkx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp4_aclkr 1 IO
spi3_sclk 2 IO 0
uart8_rxd 3 I 1
i2c4_sda 4 IO 1
vout2_d16 Yes / No 6 O
vin4a_d16 Yes / No 8 I 0
vin5a_d15 Yes / No 9 I 0
Driver off 15 I
G16 mcasp4_axr0 mcasp4_axr0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
spi3_d0 2 IO 0
uart8_ctsn 3 I 1
uart4_rxd 4 I 1
vout2_d18 Yes / No 6 O
vin4a_d18 Yes / No 8 I 0
vin5a_d13 Yes / No 9 I 0
Driver off 15 I
D17 mcasp4_axr1 mcasp4_axr1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
spi3_cs0 2 IO 1
uart8_rtsn 3 O
uart4_txd 4 O
vout2_d19 Yes / No 6 O
vin4a_d19 Yes / No 8 I 0
vin5a_d12 Yes / No 9 I 0
Driver off 15 I
A21 mcasp4_fsx mcasp4_fsx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp4_fsr 1 IO
spi3_d1 2 IO 0
uart8_txd 3 O
i2c4_scl 4 IO 1
vout2_d17 Yes / No 6 O
vin4a_d17 Yes / No 8 I 0
vin5a_d14 Yes / No 9 I 0
Driver off 15 I
AA3 mcasp5_aclkx mcasp5_aclkx 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 0
mcasp5_aclkr 1 IO
spi4_sclk 2 IO 0
uart9_rxd 3 I 1
i2c5_sda 4 IO 1
vout2_d20 Yes / No 6 O
vin4a_d20 Yes / No 8 I 0
vin5a_d11 Yes / No 9 I 0
Driver off 15 I
AB3 mcasp5_axr0 mcasp5_axr0 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 0
spi4_d0 2 IO 0
uart9_ctsn 3 I 1
uart3_rxd 4 I 1
vout2_d22 Yes / No 6 O
vin4a_d22 Yes / No 8 I 0
vin5a_d9 Yes / No 9 I 0
Driver off 15 I
AA4 mcasp5_axr1 mcasp5_axr1 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 0
spi4_cs0 2 IO 1
uart9_rtsn 3 O
uart3_txd 4 O
vout2_d23 Yes / No 6 O
vin4a_d23 Yes / No 8 I 0
vin5a_d8 Yes / No 9 I 0
Driver off 15 I
AB9 mcasp5_fsx mcasp5_fsx 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 0
mcasp5_fsr 1 IO
spi4_d1 2 IO 0
uart9_txd 3 O
i2c5_scl 4 IO 1
vout2_d21 Yes / No 6 O
vin4a_d21 Yes / No 8 I 0
vin5a_d10 Yes / No 9 I 0
Driver off 15 I
U4 mdio_d mdio_d 0 IO PU PU 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD 1
uart3_ctsn 1 I 1
mii0_txer 3 O 0
vin2a_d0 Yes / No 4 I 0
vin4b_d0 Yes / No 5 I 0
gpio5_16 14 IO
Driver off 15 I
V1 mdio_mclk mdio_mclk 0 O PU PU 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD 1
uart3_rtsn 1 O
mii0_col 3 I 0
vin2a_clk0 Yes / No 4 I
vin4b_clk1 Yes / No 5 I 0
gpio5_15 14 IO
Driver off 15 I
W6 mmc1_clk mmc1_clk 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO1833 PU/PD 1
gpio6_21 14 IO
Driver off 15 I
Y6 mmc1_cmd mmc1_cmd 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO1833 PU/PD 1
gpio6_22 14 IO
Driver off 15 I
AA6 mmc1_dat0 mmc1_dat0 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO1833 PU/PD 1
gpio6_23 14 IO
Driver off 15 I
Y4 mmc1_dat1 mmc1_dat1 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO1833 PU/PD 1
gpio6_24 14 IO
Driver off 15 I
AA5 mmc1_dat2 mmc1_dat2 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO1833 PU/PD 1
gpio6_25 14 IO
Driver off 15 I
Y3 mmc1_dat3 mmc1_dat3 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO1833 PU/PD 1
gpio6_26 14 IO
Driver off 15 I
W7 mmc1_sdcd mmc1_sdcd 0 I PU PU 15 1.8/3.3 vddshv8 Yes Dual Voltage LVCMOS PU/PD 1
uart6_rxd 3 I 1
i2c4_sda 4 IO 1
gpio6_27 14 IO
Driver off 15 I
Y9 mmc1_sdwp mmc1_sdwp 0 I PD PD 15 1.8/3.3 vddshv8 Yes Dual Voltage LVCMOS PU/PD 0
uart6_txd 3 O
i2c4_scl 4 IO 1
gpio6_28 14 IO
Driver off 15 I
AD4 mmc3_clk mmc3_clk 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 1
usb3_ulpi_d5 3 IO 0
vin2b_d7 Yes / No 4 I 0
vin5a_d7 Yes / No 9 I 0
ehrpwm2_tripzone_input 10 IO 0
gpio6_29 14 IO
Driver off 15 I
AC4 mmc3_cmd mmc3_cmd 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 1
spi3_sclk 1 IO 0
usb3_ulpi_d4 3 IO 0
vin2b_d6 Yes / No 4 I 0
vin5a_d6 Yes / No 9 I 0
eCAP2_in_PWM2_out 10 IO 0
gpio6_30 14 IO
Driver off 15 I
AC7 mmc3_dat0 mmc3_dat0 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 1
spi3_d1 1 IO 0
uart5_rxd 2 I 1
usb3_ulpi_d3 3 IO 0
vin2b_d5 Yes / No 4 I 0
vin5a_d5 Yes / No 9 I 0
eQEP3A_in 10 I 0
gpio6_31 14 IO
Driver off 15 I
AC6 mmc3_dat1 mmc3_dat1 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 1
spi3_d0 1 IO 0
uart5_txd 2 O
usb3_ulpi_d2 3 IO 0
vin2b_d4 Yes / No 4 I 0
vin5a_d4 Yes / No 9 I 0
eQEP3B_in 10 I 0
gpio7_0 14 IO
Driver off 15 I
AC9 mmc3_dat2 mmc3_dat2 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 1
spi3_cs0 1 IO 1
uart5_ctsn 2 I 1
usb3_ulpi_d1 3 IO 0
vin2b_d3 Yes / No 4 I 0
vin5a_d3 Yes / No 9 I 0
eQEP3_index 10 IO 0
gpio7_1 14 IO
Driver off 15 I
AC3 mmc3_dat3 mmc3_dat3 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 1
spi3_cs1 1 IO 1
uart5_rtsn 2 O
usb3_ulpi_d0 3 IO 0
vin2b_d2 Yes / No 4 I 0
vin5a_d2 Yes / No 9 I 0
eQEP3_strobe 10 IO 0
gpio7_2 14 IO
Driver off 15 I
AC8 mmc3_dat4 mmc3_dat4 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 1
spi4_sclk 1 IO 0
uart10_rxd 2 I 1
usb3_ulpi_nxt 3 I 0
vin2b_d1 Yes / No 4 I 0
vin5a_d1 Yes / No 9 I 0
ehrpwm3A 10 O
gpio1_22 14 IO
Driver off 15 I
AD6 mmc3_dat5 mmc3_dat5 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 1
spi4_d1 1 IO 0
uart10_txd 2 O
usb3_ulpi_dir 3 I 0
vin2b_d0 Yes / No 4 I 0
vin5a_d0 Yes / No 9 I 0
ehrpwm3B 10 O
gpio1_23 14 IO
Driver off 15 I
AB8 mmc3_dat6 mmc3_dat6 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 1
spi4_d0 1 IO 0
uart10_ctsn 2 I 1
usb3_ulpi_stp 3 O
vin2b_de1 Yes / No 4 I
vin5a_hsync0 Yes / No 9 I 0
ehrpwm3_tripzone_input 10 IO 0
gpio1_24 14 IO
Driver off 15 I
AB5 mmc3_dat7 mmc3_dat7 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 1
spi4_cs0 1 IO 1
uart10_rtsn 2 O
usb3_ulpi_clk 3 I 0
vin2b_clk1 Yes / No 4 I
vin5a_vsync0 Yes / No 9 I 0
eCAP3_in_PWM3_out 10 IO 0
gpio1_25 14 IO
Driver off 15 I
D21 nmin_dsp nmin_dsp 0 I PD PD 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
Y11 on_off on_off 0 O PU drive 1 (OFF) 1.8/3.3 vddshv5 Yes BC1833IHHV PU/PD
AG13 pcie_rxn0 pcie_rxn0 0 I OFF OFF 1.8 vdda_pcie0 SERDES
AG11 pcie_rxn1 pcie_rxn1 0 I OFF OFF 1.8 vdda_pcie1 SERDES
AH13 pcie_rxp0 pcie_rxp0 0 I OFF OFF 1.8 vdda_pcie0 SERDES
AH11 pcie_rxp1 pcie_rxp1 0 I OFF OFF 1.8 vdda_pcie1 SERDES
AG14 pcie_txn0 pcie_txn0 0 O 1.8 vdda_pcie0 SERDES
AG12 pcie_txn1 pcie_txn1 0 O 1.8 vdda_pcie1 SERDES
AH14 pcie_txp0 pcie_txp0 0 O 1.8 vdda_pcie0 SERDES
AH12 pcie_txp1 pcie_txp1 0 O 1.8 vdda_pcie1 SERDES
F22 porz porz 0 I 1.8/3.3 vddshv3 Yes IHHV1833 PU/PD
E23 resetn resetn 0 I PU PU 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
U5 rgmii0_rxc rgmii0_rxc 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD 0
rmii1_txen 2 O
mii0_txclk 3 I 0
vin2a_d5 Yes / No 4 I 0
vin4b_d5 Yes / No 5 I 0
usb4_ulpi_d2 6 IO 0
gpio5_26 14 IO
Driver off 15 I
V5 rgmii0_rxctl rgmii0_rxctl 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD 0
rmii1_txd1 2 O
mii0_txd3 3 O
vin2a_d6 Yes / No 4 I 0
vin4b_d6 Yes / No 5 I 0
usb4_ulpi_d3 6 IO 0
gpio5_27 14 IO
Driver off 15 I
W2 rgmii0_rxd0 rgmii0_rxd0 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD 0
rmii0_txd0 1 O
mii0_txd0 3 O
vin2a_fld0 Yes / No 4 I
vin4b_fld1 Yes / No 5 I 0
usb4_ulpi_d7 6 IO 0
gpio5_31 14 IO
Driver off 15 I
Y2 rgmii0_rxd1 rgmii0_rxd1 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD 0
rmii0_txd1 1 O
mii0_txd1 3 O
vin2a_d9 Yes / No 4 I 0
usb4_ulpi_d6 6 IO 0
gpio5_30 14 IO
Driver off 15 I
V3 rgmii0_rxd2 rgmii0_rxd2 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD 0
rmii0_txen 1 O
mii0_txen 3 O
vin2a_d8 Yes / No 4 I 0
usb4_ulpi_d5 6 IO 0
gpio5_29 14 IO
Driver off 15 I
V4 rgmii0_rxd3 rgmii0_rxd3 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD 0
rmii1_txd0 2 O
mii0_txd2 3 O
vin2a_d7 Yes / No 4 I 0
vin4b_d7 Yes / No 5 I 0
usb4_ulpi_d4 6 IO 0
gpio5_28 14 IO
Driver off 15 I
W9 rgmii0_txc rgmii0_txc 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
uart3_ctsn 1 I 1
rmii1_rxd1 2 I 0
mii0_rxd3 3 I 0
vin2a_d3 Yes / No 4 I 0
vin4b_d3 Yes / No 5 I 0
usb4_ulpi_clk 6 I 0
spi3_d0 7 IO 0
spi4_cs2 8 IO 1
gpio5_20 14 IO
Driver off 15 I
V9 rgmii0_txctl rgmii0_txctl 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
uart3_rtsn 1 O
rmii1_rxd0 2 I 0
mii0_rxd2 3 I 0
vin2a_d4 Yes / No 4 I 0
vin4b_d4 Yes / No 5 I 0
usb4_ulpi_stp 6 O
spi3_cs0 7 IO 1
spi4_cs3 8 IO 1
gpio5_21 14 IO
Driver off 15 I
U6 rgmii0_txd0 rgmii0_txd0 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii0_rxd0 1 I 0
mii0_rxd0 3 I 0
vin2a_d10 Yes / No 4 I 0
usb4_ulpi_d1 6 IO 0
spi4_cs0 7 IO 1
uart4_rtsn 8 O
gpio5_25 14 IO
Driver off 15 I
V6 rgmii0_txd1 rgmii0_txd1 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii0_rxd1 1 I 0
mii0_rxd1 3 I 0
vin2a_vsync0 Yes / No 4 I
vin4b_vsync1 Yes / No 5 I 0
usb4_ulpi_d0 6 IO 0
spi4_d0 7 IO 0
uart4_ctsn 8 IO 1
gpio5_24 14 IO
Driver off 15 I
U7 rgmii0_txd2 rgmii0_txd2 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii0_rxer 1 I 0
mii0_rxer 3 I 0
vin2a_hsync0 Yes / No 4 I
vin4b_hsync1 Yes / No 5 I 0
usb4_ulpi_nxt 6 I 0
spi4_d1 7 IO 0
uart4_txd 8 O
gpio5_23 14 IO
Driver off 15 I
V7 rgmii0_txd3 rgmii0_txd3 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii0_crs 1 I 0
mii0_crs 3 I 0
vin2a_de0 Yes / No 4 I
vin4b_de1 Yes / No 5 I 0
usb4_ulpi_dir 6 I 0
spi4_sclk 7 IO 0
uart4_rxd 8 I 1
gpio5_22 14 IO
Driver off 15 I
U3 RMII_MHZ_50_CLK RMII_MHZ_50_CLK 0 IO PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD 0
vin2a_d11 Yes / No 4 I 0
gpio5_17 14 IO
Driver off 15 I
F23 rstoutn rstoutn 0 O PD drive 1 (OFF) 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
E18 rtck rtck 0 O PU drive clk (OFF) 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio8_29 14 IO
AF14 rtc_iso rtc_iso 0 I 1.8/3.3 vddshv5 Yes IHHV1833 PU/PD
AE14 rtc_osc_xi_clkin32 rtc_osc_xi_clkin32 0 I 1.8 vdda_rtc No LVCMOS OSC
AD14 rtc_osc_xo rtc_osc_xo 0 O 1.8 vdda_rtc No LVCMOS OSC
AB17 rtc_porz rtc_porz 0 I 1.8/3.3 vddshv5 Yes IHHV1833 PU/PD
AH9 sata1_rxn0 sata1_rxn0 0 I OFF OFF 1.8 vdda_sata SATAPHY
AG9 sata1_rxp0 sata1_rxp0 0 I OFF OFF 1.8 vdda_sata SATAPHY
AG10 sata1_txn0 sata1_txn0 0 O 1.8 vdda_sata SATAPHY
AH10 sata1_txp0 sata1_txp0 0 O 1.8 vdda_sata SATAPHY
A24 spi1_cs0 spi1_cs0 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 1
gpio7_10 14 IO
Driver off 15 I
A22 spi1_cs1 spi1_cs1 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 1
sata1_led 2 O
spi2_cs1 3 IO 1
gpio7_11 14 IO
Driver off 15 I
B21 spi1_cs2 spi1_cs2 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 1
uart4_rxd 1 I 1
mmc3_sdcd 2 I 1
spi2_cs2 3 IO 1
dcan2_tx 4 IO 1
mdio_mclk 5 O 1
hdmi1_hpd Yes / No 6 I
gpio7_12 14 IO
Driver off 15 I
B20 spi1_cs3 spi1_cs3 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 1
uart4_txd 1 O
mmc3_sdwp 2 I 0
spi2_cs3 3 IO 1
dcan2_rx 4 IO 1
mdio_d 5 IO 1
hdmi1_cec Yes / No 6 IO
gpio7_13 14 IO
Driver off 15 I
B25 spi1_d0 spi1_d0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
gpio7_9 14 IO
Driver off 15 I
F16 spi1_d1 spi1_d1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
gpio7_8 14 IO
Driver off 15 I
A25 spi1_sclk spi1_sclk 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
gpio7_7 14 IO
Driver off 15 I
B24 spi2_cs0 spi2_cs0 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 1
uart3_rtsn 1 O
uart5_txd 2 O
gpio7_17 14 IO
Driver off 15 I
G17 spi2_d0 spi2_d0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
uart3_ctsn 1 I 1
uart5_rxd 2 I 1
gpio7_16 14 IO
Driver off 15 I
B22 spi2_d1 spi2_d1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
uart3_txd 1 O
gpio7_15 14 IO
Driver off 15 I
A26 spi2_sclk spi2_sclk 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
uart3_rxd 1 I 1
gpio7_14 14 IO
Driver off 15 I
E20 tclk tclk 0 I PU PU 0 1.8/3.3 vddshv3 Yes IQ1833 PU/PD
D23 tdi tdi 0 I PU PU 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio8_27 14 I
F19 tdo tdo 0 O PU PU 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio8_28 14 IO
F18 tms tms 0 IO OFF OFF 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
D20 trstn trstn 0 I PD PD 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
E25 uart1_ctsn uart1_ctsn 0 I PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD 1
uart9_rxd 2 I 1
mmc4_clk 3 IO 1
gpio7_24 14 IO
Driver off 15 I
C27 uart1_rtsn uart1_rtsn 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
uart9_txd 2 O
mmc4_cmd 3 IO 1
gpio7_25 14 IO
Driver off 15 I
B27 uart1_rxd uart1_rxd 0 I PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD 1
mmc4_sdcd 3 I 1
gpio7_22 14 IO
Driver off 15 I
C26 uart1_txd uart1_txd 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
mmc4_sdwp 3 I 0
gpio7_23 14 IO
Driver off 15 I
D27 uart2_ctsn uart2_ctsn 0 I PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD 1
uart3_rxd 2 I 1
mmc4_dat2 3 IO 1
uart10_rxd 4 I 1
uart1_dtrn 5 O
gpio1_16 14 IO
Driver off 15 I
C28 uart2_rtsn uart2_rtsn 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
uart3_txd 1 O
uart3_irtx 2 O
mmc4_dat3 3 IO 1
uart10_txd 4 O
uart1_rin 5 I 1
gpio1_17 14 IO
Driver off 15 I
D28 uart2_rxd uart3_ctsn 1 I PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD 1
uart3_rctx 2 O
mmc4_dat0 3 IO 1
uart2_rxd 4 I 1
uart1_dcdn 5 I 1
gpio7_26 14 IO
Driver off 15 I
D26 uart2_txd uart2_txd 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
uart3_rtsn 1 O
uart3_sd 2 O
mmc4_dat1 3 IO 1
uart2_txd 4 O
uart1_dsrn 5 I 0
gpio7_27 14 IO
Driver off 15 I
V2 uart3_rxd uart3_rxd 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD 1
rmii1_crs 2 I 0
mii0_rxdv 3 I 0
vin2a_d1 Yes / No 4 I 0
vin4b_d1 Yes / No 5 I 0
spi3_sclk 7 IO 0
gpio5_18 14 IO
Driver off 15 I
Y1 uart3_txd uart3_txd 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii1_rxer 2 I 0
mii0_rxclk 3 I 0
vin2a_d2 Yes / No 4 I 0
vin4b_d2 Yes / No 5 I 0
spi3_d1 7 IO 0
spi4_cs1 8 IO 1
gpio5_19 14 IO
Driver off 15 I
AC12 usb1_dm usb1_dm 0 IO OFF OFF 3.3 vdda33v_usb1 USB3PHY
AD12 usb1_dp usb1_dp 0 IO OFF OFF 3.3 vdda33v_usb1 USB3PHY
AB10 usb1_drvvbus usb1_drvvbus 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
timer16 7 IO
gpio6_12 14 IO
Driver off 15 I
AF11 usb2_dm usb2_dm 0 IO 3.3 vdda33v_usb2 No USB2PHY
AE11 usb2_dp usb2_dp 0 IO 3.3 vdda33v_usb2 No USB2PHY
AC10 usb2_drvvbus usb2_drvvbus 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
timer15 7 IO
gpio6_13 14 IO
Driver off 15 I
AF12 usb_rxn0 usb_rxn0 0 I OFF OFF 1.8 vdda_usb1
AE12 usb_rxp0 usb_rxp0 0 I OFF OFF 1.8 vdda_usb1
AC11 usb_txn0 usb_txn0 0 O 1.8 vdda_usb1
AD11 usb_txp0 usb_txp0 0 O 1.8 vdda_usb1
H13, H14, J17, J18, L7, L8, N10, N13, P11, P12, P13, R11, R16, R19, T13, T16, T19, U13, U16, U8, U9, V16, V8 vdd vdd PWR
AA12 vdda33v_usb1 vdda33v_usb1 PWR
Y12 vdda33v_usb2 vdda33v_usb2 PWR
M14 vdda_abe_per vdda_abe_per PWR
P16 vdda_ddr vdda_ddr PWR
N11 vdda_debug vdda_debug PWR
N12 vdda_dsp_eve vdda_dsp_eve PWR
P15 vdda_gmac_core vdda_gmac_core PWR
R14 vdda_gpu vdda_gpu PWR
Y17 vdda_hdmi vdda_hdmi PWR
R17 vdda_iva vdda_iva PWR
N16 vdda_mpu vdda_mpu PWR
AD16, AE16 vdda_osc vdda_osc PWR
AA17 vdda_pcie0 vdda_pcie0 PWR
W14 vdda_pcie vdda_pcie PWR
AA16 vdda_pcie1 vdda_pcie1 PWR
AB13 vdda_rtc vdda_rtc PWR
V13 vdda_sata vdda_sata PWR
AA13 vdda_usb1 vdda_usb1 PWR
AB12 vdda_usb2 vdda_usb2 PWR
W12 vdda_usb3 vdda_usb3 PWR
P14 vdda_video vdda_video PWR
G18, H17, M8, M9, N8, P8, R8, T8, V21, V22, W17, W18 vdds18v vdds18v PWR
AA18, AA19, W21, Y21 vdds18v_ddr1 vdds18v_ddr1 PWR
J21, J22, N21, P20, P21 vdds18v_ddr2 vdds18v_ddr2 PWR
E3, E5, G4, G5, H8, H9 vddshv1 vddshv1 PWR
B6, D10, E10, H10, H11 vddshv2 vddshv2 PWR
B23, D16, D22, E16, E22, G15, H15, H16, H18, H19 vddshv3 vddshv3 PWR
C24 vddshv4 vddshv4 PWR
V12 vddshv5 vddshv5 PWR
AD5, AD7, AE7, AF5 vddshv6 vddshv6 PWR
AB6, AB7 vddshv7 vddshv7 PWR
W8, Y8 vddshv8 vddshv8 PWR
U10, W4, W5 vddshv9 vddshv9 PWR
N4, N5, P10, R10, R7, T4, T5 vddshv10 vddshv10 PWR
J8, K8 vddshv11 vddshv11 PWR
AA21, AA22, AB21, AB22, AB24, AB25, AC22, AD26, AG20, AG28, AH27, W16, W27 vdds_ddr1 vdds_ddr1 PWR
E24, G22, G23, H20, H21, H22, J27, L20, L21, M20, M21, T24, T25 vdds_ddr2 vdds_ddr2 PWR
AA7, Y7 vdds_mlbp vdds_mlbp PWR
J13, K10, K11, K12, K13, L10, L11, L12, M10, M11, M12, M13 vdd_dspeve vdd_dspeve PWR
U11, U12, V10, V11, V14, W10, W11, W13 vdd_gpu vdd_gpu PWR
U18, U19, V18, V19 vdd_iva vdd_iva PWR
K17, K18, L15, L16, L17, L18, L19, M15, M16, M17, M18, N17, N18, P17, P18, R18 vdd_mpu vdd_mpu PWR
AB15 vdd_rtc vdd_rtc PWR
AG8 vin1a_clk0 vin1a_clk0 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vout3_d16(8) Yes / No 3 O
vout3_fld(8) Yes / No 4 O
gpio2_30 14 IO
Driver off 15 I
AE8 vin1a_d0 vin1a_d0 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vout3_d7(8) Yes / No 3 O
vout3_d23(8) Yes / No 4 O
uart8_rxd 5 I 1
ehrpwm1A 10 O
gpio3_4 14 IO
Driver off 15 I
AD8 vin1a_d1 vin1a_d1 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vout3_d6(8) Yes / No 3 O
vout3_d22(8) Yes / No 4 O
uart8_txd 5 O
ehrpwm1B 10 O
gpio3_5 14 IO
Driver off 15 I
AG7 vin1a_d2 vin1a_d2 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vout3_d5(8) Yes / No 3 O
vout3_d21(8) Yes / No 4 O
uart8_ctsn 5 I 1
ehrpwm1_tripzone_input 10 IO 0
gpio3_6 14 IO
Driver off 15 I
AH6 vin1a_d3 vin1a_d3 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vout3_d4(8) Yes / No 3 O
vout3_d20(8) Yes / No 4 O
uart8_rtsn 5 O
eCAP1_in_PWM1_out 10 IO 0
gpio3_7 14 IO
Driver off 15 I
AH3 vin1a_d4 vin1a_d4 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vout3_d3(8) Yes / No 3 O
vout3_d19(8) Yes / No 4 O
ehrpwm1_synci 10 I 0
gpio3_8 14 IO
Driver off 15 I
AH5 vin1a_d5 vin1a_d5 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vout3_d2(8) Yes / No 3 O
vout3_d18(8) Yes / No 4 O
ehrpwm1_synco 10 O
gpio3_9 14 IO
Driver off 15 I
AG6 vin1a_d6 vin1a_d6 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vout3_d1(8) Yes / No 3 O
vout3_d17(8) Yes / No 4 O
eQEP2A_in 10 I 0
gpio3_10 14 IO
Driver off 15 I
AH4 vin1a_d7 vin1a_d7 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vout3_d0(8) Yes / No 3 O
vout3_d16(8) Yes / No 4 O
eQEP2B_in 10 I 0
gpio3_11 14 IO
Driver off 15 I
AG4 vin1a_d8 vin1a_d8 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vin1b_d7 Yes / No 1 I 0
vout3_d15(8) Yes / No 4 O
eQEP2_index 10 IO 0
gpio3_12 14 IO
Driver off 15 I
AG2 vin1a_d9 vin1a_d9 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vin1b_d6 Yes / No 1 I 0
vout3_d14(8) Yes / No 4 O
eQEP2_strobe 10 IO 0
gpio3_13 14 IO
Driver off 15 I
AG3 vin1a_d10 vin1a_d10 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vin1b_d5 Yes / No 1 I 0
vout3_d13(8) Yes / No 4 O
gpio3_14 14 IO
Driver off 15 I
AG5 vin1a_d11 vin1a_d11 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vin1b_d4 Yes / No 1 I 0
vout3_d12(8) Yes / No 4 O
gpmc_a23 5 O
gpio3_15 14 IO
Driver off 15 I
AF2 vin1a_d12 vin1a_d12 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vin1b_d3 Yes / No 1 I 0
usb3_ulpi_d7 2 IO 0
vout3_d11(8) Yes / No 4 O
gpmc_a24 5 O
gpio3_16 14 IO
Driver off 15 I
AF6 vin1a_d13 vin1a_d13 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vin1b_d2 Yes / No 1 I 0
usb3_ulpi_d6 2 IO 0
vout3_d10(8) Yes / No 4 O
gpmc_a25 5 O
gpio3_17 14 IO
Driver off 15 I
AF3 vin1a_d14 vin1a_d14 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vin1b_d1 Yes / No 1 I 0
usb3_ulpi_d5 2 IO 0
vout3_d9(8) Yes / No 4 O
gpmc_a26 5 O
gpio3_18 14 IO
Driver off 15 I
AF4 vin1a_d15 vin1a_d15 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vin1b_d0 Yes / No 1 I 0
usb3_ulpi_d4 2 IO 0
vout3_d8(8) Yes / No 4 O
gpmc_a27 5 O
gpio3_19 14 IO
Driver off 15 I
AF1 vin1a_d16 vin1a_d16 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vin1b_d7 Yes / No 1 I 0
usb3_ulpi_d3 2 IO 0
vout3_d7(8) Yes / No 4 O
vin3a_d0 Yes / No 6 I 0
gpio3_20 14 IO
Driver off 15 I
AE3 vin1a_d17 vin1a_d17 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vin1b_d6 Yes / No 1 I 0
usb3_ulpi_d2 2 IO 0
vout3_d6(8) Yes / No 4 O
vin3a_d1 Yes / No 6 I 0
gpio3_21 14 IO
Driver off 15 I
AE5 vin1a_d18 vin1a_d18 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vin1b_d5 Yes / No 1 I 0
usb3_ulpi_d1 2 IO 0
vout3_d5(8) Yes / No 4 O
vin3a_d2 Yes / No 6 I 0
gpio3_22 14 IO
Driver off 15 I
AE1 vin1a_d19 vin1a_d19 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vin1b_d4 Yes / No 1 I 0
usb3_ulpi_d0 2 IO 0
vout3_d4(8) Yes / No 4 O
vin3a_d3 Yes / No 6 I 0
gpio3_23 14 IO
Driver off 15 I
AE2 vin1a_d20 vin1a_d20 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vin1b_d3 Yes / No 1 I 0
usb3_ulpi_nxt 2 I 0
vout3_d3(8) Yes / No 4 O
vin3a_d4 Yes / No 6 I 0
gpio3_24 14 IO
Driver off 15 I
AE6 vin1a_d21 vin1a_d21 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vin1b_d2 Yes / No 1 I 0
usb3_ulpi_dir 2 I 0
vout3_d2(8) Yes / No 4 O
vin3a_d5 Yes / No 6 I 0
gpio3_25 14 IO
Driver off 15 I
AD2 vin1a_d22 vin1a_d22 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vin1b_d1 Yes / No 1 I 0
usb3_ulpi_stp 2 O
vout3_d1(8) Yes / No 4 O
vin3a_d6 Yes / No 6 I 0
gpio3_26 14 IO
Driver off 15 I
AD3 vin1a_d23 vin1a_d23 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vin1b_d0 Yes / No 1 I 0
usb3_ulpi_clk 2 I 0
vout3_d0(8) Yes / No 4 O
vin3a_d7 Yes / No 6 I 0
gpio3_27 14 IO
Driver off 15 I
AD9 vin1a_de0 vin1a_de0 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vin1b_hsync1 Yes / No 1 I 0
vout3_d17(8) Yes / No 3 O
vout3_de(8) Yes / No 4 O
uart7_rxd 5 I 1
timer16 7 IO
spi3_sclk 8 IO 0
eQEP1A_in 10 I 0
gpio3_0 14 IO
Driver off 15 I
AF9 vin1a_fld0 vin1a_fld0 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vin1b_vsync1 Yes / No 1 I 0
vout3_clk(8) Yes / No 4 O
uart7_txd 5 O
timer15 7 IO
spi3_d1 8 IO 0
eQEP1B_in 10 I 0
gpio3_1 14 IO
Driver off 15 I
AE9 vin1a_hsync0 vin1a_hsync0 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vin1b_fld1 Yes / No 1 I 0
vout3_hsync(8) Yes / No 4 O
uart7_ctsn 5 I 1
timer14 7 IO
spi3_d0 8 IO 0
eQEP1_index 10 IO 0
gpio3_2 14 IO
Driver off 15 I
AF8 vin1a_vsync0 vin1a_vsync0 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vin1b_de1 Yes / No 1 I 0
vout3_vsync(8) Yes / No 4 O
uart7_rtsn 5 O
timer13 7 IO
spi3_cs0 8 IO 1
eQEP1_strobe 10 IO 0
gpio3_3 14 IO
Driver off 15 I
AH7 vin1b_clk1 vin1b_clk1 Yes / No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 0
vin3a_clk0 Yes / No 6 I 0
gpio2_31 14 IO
Driver off 15 I
E1 vin2a_clk0 vin2a_clk0 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_fld Yes / No 4 O
emu5 5 O
eQEP1A_in 10 I 0
gpio3_28 14 IO
Driver off 15 I
F2 vin2a_d0 vin2a_d0 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vout2_d23 Yes / No 4 O
emu10 5 O
uart9_ctsn 7 I 1
spi4_d0 8 IO 0
ehrpwm1B 10 O
gpio4_1 14 IO
Driver off 15 I
F3 vin2a_d1 vin2a_d1 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vout2_d22 Yes / No 4 O
emu11 5 O
uart9_rtsn 7 O
spi4_cs0 8 IO 1
ehrpwm1_tripzone_input 10 IO 0
gpio4_2 14 IO
Driver off 15 I
D1 vin2a_d2 vin2a_d2 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vout2_d21 Yes / No 4 O
emu12 5 O
uart10_rxd 8 I 1
eCAP1_in_PWM1_out 10 IO 0
gpio4_3 14 IO
Driver off 15 I
E2 vin2a_d3 vin2a_d3 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vout2_d20 Yes / No 4 O
emu13 5 O
uart10_txd 8 O
ehrpwm1_synci 10 I 0
gpio4_4 14 IO
Driver off 15 I
D2 vin2a_d4 vin2a_d4 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vout2_d19 Yes / No 4 O
emu14 5 O
uart10_ctsn 8 I 1
ehrpwm1_synco 10 O
gpio4_5 14 IO
Driver off 15 I
F4 vin2a_d5 vin2a_d5 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vout2_d18 Yes / No 4 O
emu15 5 O
uart10_rtsn 8 O
eQEP2A_in 10 I 0
gpio4_6 14 IO
Driver off 15 I
C1 vin2a_d6 vin2a_d6 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vout2_d17 Yes / No 4 O
emu16 5 O
mii1_rxd1 8 I 0
eQEP2B_in 10 I 0
gpio4_7 14 IO
Driver off 15 I
E4 vin2a_d7 vin2a_d7 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vout2_d16 Yes / No 4 O
emu17 5 O
mii1_rxd2 8 I 0
eQEP2_index 10 IO 0
gpio4_8 14 IO
Driver off 15 I
F5 vin2a_d8 vin2a_d8 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vout2_d15 Yes / No 4 O
emu18 5 O
mii1_rxd3 8 I 0
eQEP2_strobe 10 IO 0
gpio4_9 14 IO
Driver off 15 I
E6 vin2a_d9 vin2a_d9 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vout2_d14 Yes / No 4 O
emu19 5 O
mii1_rxd0 8 I 0
ehrpwm2A 10 O
gpio4_10 14 IO
Driver off 15 I
D3 vin2a_d10 vin2a_d10 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
mdio_mclk 3 O 1
vout2_d13 Yes / No 4 O
ehrpwm2B 10 O
gpio4_11 14 IO
Driver off 15 I
F6 vin2a_d11 vin2a_d11 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
mdio_d 3 IO 1
vout2_d12 Yes / No 4 O
ehrpwm2_tripzone_input 10 IO 0
gpio4_12 14 IO
Driver off 15 I
D5 vin2a_d12 vin2a_d12 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
rgmii1_txc 3 O
vout2_d11 Yes / No 4 O
mii1_rxclk 8 I 0
eCAP2_in_PWM2_out 10 IO 0
gpio4_13 14 IO
Driver off 15 I
C2 vin2a_d13 vin2a_d13 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
rgmii1_txctl 3 O
vout2_d10 Yes / No 4 O
mii1_rxdv 8 I 0
eQEP3A_in 10 I 0
gpio4_14 14 IO
Driver off 15 I
C3 vin2a_d14 vin2a_d14 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
rgmii1_txd3 3 O
vout2_d9 Yes / No 4 O
mii1_txclk 8 I 0
eQEP3B_in 10 I 0
gpio4_15 14 IO
Driver off 15 I
C4 vin2a_d15 vin2a_d15 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
rgmii1_txd2 3 O
vout2_d8 Yes / No 4 O
mii1_txd0 8 O
eQEP3_index 10 IO 0
gpio4_16 14 IO
Driver off 15 I
B2 vin2a_d16 vin2a_d16 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vin2b_d7 Yes / No 2 I 0
rgmii1_txd1 3 O
vout2_d7 Yes / No 4 O
vin3a_d8 Yes / No 6 I 0
mii1_txd1 8 O
eQEP3_strobe 10 IO 0
gpio4_24 14 IO
Driver off 15 I
D6 vin2a_d17 vin2a_d17 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vin2b_d6 Yes / No 2 I 0
rgmii1_txd0 3 O
vout2_d6 Yes / No 4 O
vin3a_d9 Yes / No 6 I 0
mii1_txd2 8 O
ehrpwm3A 10 O
gpio4_25 14 IO
Driver off 15 I
C5 vin2a_d18 vin2a_d18 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vin2b_d5 Yes / No 2 I 0
rgmii1_rxc 3 I 0
vout2_d5 Yes / No 4 O
vin3a_d10 Yes / No 6 I 0
mii1_txd3 8 O
ehrpwm3B 10 O
gpio4_26 14 IO
Driver off 15 I
A3 vin2a_d19 vin2a_d19 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vin2b_d4 Yes / No 2 I 0
rgmii1_rxctl 3 I 0
vout2_d4 Yes / No 4 O
vin3a_d11 Yes / No 6 I 0
mii1_txer 8 O 0
ehrpwm3_tripzone_input 10 IO 0
gpio4_27 14 IO
Driver off 15 I
B3 vin2a_d20 vin2a_d20 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vin2b_d3 Yes / No 2 I 0
rgmii1_rxd3 3 I 0
vout2_d3 Yes / No 4 O
vin3a_de0 Yes / No 5 I 0
vin3a_d12 Yes / No 6 I 0
mii1_rxer 8 I 0
eCAP3_in_PWM3_out 10 IO 0
gpio4_28 14 IO
Driver off 15 I
B4 vin2a_d21 vin2a_d21 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vin2b_d2 Yes / No 2 I 0
rgmii1_rxd2 3 I 0
vout2_d2 Yes / No 4 O
vin3a_fld0 Yes / No 5 I 0
vin3a_d13 Yes / No 6 I 0
mii1_col 8 I 0
gpio4_29 14 IO
Driver off 15 I
B5 vin2a_d22 vin2a_d22 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vin2b_d1 Yes / No 2 I 0
rgmii1_rxd1 3 I 0
vout2_d1 Yes / No 4 O
vin3a_hsync0 Yes / No 5 I 0
vin3a_d14 Yes / No 6 I 0
mii1_crs 8 I 0
gpio4_30 14 IO
Driver off 15 I
A4 vin2a_d23 vin2a_d23 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vin2b_d0 Yes / No 2 I 0
rgmii1_rxd0 3 I 0
vout2_d0 Yes / No 4 O
vin3a_vsync0 Yes / No 5 I 0
vin3a_d15 Yes / No 6 I 0
mii1_txen 8 O
gpio4_31 14 IO
Driver off 15 I
G2 vin2a_de0 vin2a_de0 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2a_fld0 Yes / No 1 I
vin2b_fld1 Yes / No 2 I
vin2b_de1 Yes / No 3 I
vout2_de Yes / No 4 O
emu6 5 O
eQEP1B_in 10 I 0
gpio3_29 14 IO
Driver off 15 I
H7 vin2a_fld0 vin2a_fld0 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_clk1 Yes / No 2 I
vout2_clk Yes / No 4 O
emu7 5 O
eQEP1_index 10 IO 0
gpio3_30 14 IO
Driver off 15 I
G1 vin2a_hsync0 vin2a_hsync0 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_hsync1 Yes / No 3 I
vout2_hsync Yes / No 4 O
emu8 5 O
uart9_rxd 7 I 1
spi4_sclk 8 IO 0
eQEP1_strobe 10 IO 0
gpio3_31 14 IO
Driver off 15 I
G6 vin2a_vsync0 vin2a_vsync0 Yes / No 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_vsync1 Yes / No 3 I
vout2_vsync Yes / No 4 O
emu9 5 O
uart9_txd 7 O
spi4_d1 8 IO 0
ehrpwm1A 10 O
gpio4_0 14 IO
Driver off 15 I
D11 vout1_clk vout1_clk Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
vin4a_fld0 Yes / No 3 I 0
vin3a_fld0 Yes / No 4 I 0
spi3_cs0 8 IO 1
gpio4_19 14 IO
Driver off 15 I
F11 vout1_d0 vout1_d0 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
uart5_rxd 2 I 1
vin4a_d16 Yes / No 3 I 0
vin3a_d16 Yes / No 4 I 0
spi3_cs2 8 IO 1
gpio8_0 14 IO
Driver off 15 I
G10 vout1_d1 vout1_d1 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
uart5_txd 2 O
vin4a_d17 Yes / No 3 I 0
vin3a_d17 Yes / No 4 I 0
gpio8_1 14 IO
Driver off 15 I
F10 vout1_d2 vout1_d2 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu2 2 O
vin4a_d18 Yes / No 3 I 0
vin3a_d18 Yes / No 4 I 0
obs0 5 O
obs16 6 O
obs_irq1 7 O
gpio8_2 14 IO
Driver off 15 I
G11 vout1_d3 vout1_d3 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu5 2 O
vin4a_d19 Yes / No 3 I 0
vin3a_d19 Yes / No 4 I 0
obs1 5 O
obs17 6 O
obs_dmarq1 7 O
gpio8_3 14 IO
Driver off 15 I
E9 vout1_d4 vout1_d4 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu6 2 O
vin4a_d20 Yes / No 3 I 0
vin3a_d20 Yes / No 4 I 0
obs2 5 O
obs18 6 O
gpio8_4 14 IO
Driver off 15 I
F9 vout1_d5 vout1_d5 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu7 2 O
vin4a_d21 Yes / No 3 I 0
vin3a_d21 Yes / No 4 I 0
obs3 5 O
obs19 6 O
gpio8_5 14 IO
Driver off 15 I
F8 vout1_d6 vout1_d6 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu8 2 O
vin4a_d22 Yes / No 3 I 0
vin3a_d22 Yes / No 4 I 0
obs4 5 O
obs20 6 O
gpio8_6 14 IO
Driver off 15 I
E7 vout1_d7 vout1_d7 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu9 2 O
vin4a_d23 Yes / No 3 I 0
vin3a_d23 Yes / No 4 I 0
gpio8_7 14 IO
Driver off 15 I
E8 vout1_d8 vout1_d8 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
uart6_rxd 2 I 1
vin4a_d8 Yes / No 3 I 0
vin3a_d8 Yes / No 4 I 0
gpio8_8 14 IO
Driver off 15 I
D9 vout1_d9 vout1_d9 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
uart6_txd 2 O
vin4a_d9 Yes / No 3 I 0
vin3a_d9 Yes / No 4 I 0
gpio8_9 14 IO
Driver off 15 I
D7 vout1_d10 vout1_d10 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu3 2 O
vin4a_d10 Yes / No 3 I 0
vin3a_d10 Yes / No 4 I 0
obs5 5 O
obs21 6 O
obs_irq2 7 O
gpio8_10 14 IO
Driver off 15 I
D8 vout1_d11 vout1_d11 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu10 2 O
vin4a_d11 Yes / No 3 I 0
vin3a_d11 Yes / No 4 I 0
obs6 5 O
obs22 6 O
obs_dmarq2 7 O
gpio8_11 14 IO
Driver off 15 I
A5 vout1_d12 vout1_d12 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu11 2 O
vin4a_d12 Yes / No 3 I 0
vin3a_d12 Yes / No 4 I 0
obs7 5 O
obs23 6 O
gpio8_12 14 IO
Driver off 15 I
C6 vout1_d13 vout1_d13 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu12 2 O
vin4a_d13 Yes / No 3 I 0
vin3a_d13 Yes / No 4 I 0
obs8 5 O
obs24 6 O
gpio8_13 14 IO
Driver off 15 I
C8 vout1_d14 vout1_d14 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu13 2 O
vin4a_d14 Yes / No 3 I 0
vin3a_d14 Yes / No 4 I 0
obs9 5 O
obs25 6 O
gpio8_14 14 IO
Driver off 15 I
C7 vout1_d15 vout1_d15 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu14 2 O
vin4a_d15 Yes / No 3 I 0
vin3a_d15 Yes / No 4 I 0
obs10 5 O
obs26 6 O
gpio8_15 14 IO
Driver off 15 I
B7 vout1_d16 vout1_d16 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
uart7_rxd 2 I 1
vin4a_d0 Yes / No 3 I 0
vin3a_d0 Yes / No 4 I 0
gpio8_16 14 IO
Driver off 15 I
B8 vout1_d17 vout1_d17 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
uart7_txd 2 O
vin4a_d1 Yes / No 3 I 0
vin3a_d1 Yes / No 4 I 0
gpio8_17 14 IO
Driver off 15 I
A7 vout1_d18 vout1_d18 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu4 2 O
vin4a_d2 Yes / No 3 I 0
vin3a_d2 Yes / No 4 I 0
obs11 5 O
obs27 6 O
gpio8_18 14 IO
Driver off 15 I
A8 vout1_d19 vout1_d19 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu15 2 O
vin4a_d3 Yes / No 3 I 0
vin3a_d3 Yes / No 4 I 0
obs12 5 O
obs28 6 O
gpio8_19 14 IO
Driver off 15 I
C9 vout1_d20 vout1_d20 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu16 2 O
vin4a_d4 Yes / No 3 I 0
vin3a_d4 Yes / No 4 I 0
obs13 5 O
obs29 6 O
gpio8_20 14 IO
Driver off 15 I
A9 vout1_d21 vout1_d21 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu17 2 O
vin4a_d5 Yes / No 3 I 0
vin3a_d5 Yes / No 4 I 0
obs14 5 O
obs30 6 O
gpio8_21 14 IO
Driver off 15 I
B9 vout1_d22 vout1_d22 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu18 2 O
vin4a_d6 Yes / No 3 I 0
vin3a_d6 Yes / No 4 I 0
obs15 5 O
obs31 6 O
gpio8_22 14 IO
Driver off 15 I
A10 vout1_d23 vout1_d23 Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu19 2 O
vin4a_d7 Yes / No 3 I 0
vin3a_d7 Yes / No 4 I 0
spi3_cs3 8 IO 1
gpio8_23 14 IO
Driver off 15 I
B10 vout1_de vout1_de Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
vin4a_de0 Yes / No 3 I 0
vin3a_de0 Yes / No 4 I 0
spi3_d1 8 IO 0
gpio4_20 14 IO
Driver off 15 I
B11 vout1_fld vout1_fld Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
vin4a_clk0 Yes / No 3 I 0
vin3a_clk0 Yes / No 4 I 0
spi3_cs1 8 IO 1
gpio4_21 14 IO
Driver off 15 I
C11 vout1_hsync vout1_hsync Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
vin4a_hsync0 Yes / No 3 I 0
vin3a_hsync0 Yes / No 4 I 0
spi3_d0 8 IO 0
gpio4_22 14 IO
Driver off 15 I
E11 vout1_vsync vout1_vsync Yes / No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
vin4a_vsync0 Yes / No 3 I 0
vin3a_vsync0 Yes / No 4 I 0
spi3_sclk 8 IO 0
gpio4_23 14 IO
Driver off 15 I
A1, A14, A2, A23, A28, A6, AA10, AA14, AA15, AA20, AA8, AA9, AB14, AB20, AD1, AD24, AG1, AH1, AH2, AH20, AH28, AH8, B1, D13, D19, E13, E19, F1, F7, G7, G8, G9, H12, J12, J15, J28, K1, K15, K24, K25, K4, K5, L13, L14, M19, N14, N15, N19, N24, N25, P28, R1, R12, R13, R15, R21, T10, T11, T12, T14, T15, T17, T18, T21, U15, U17, U20, U21, V15, V17, W1, W15, W24, W25, W28 vss vss GND
AD19, AE19 vssa_hdmi vssa_hdmi GND
AF15 vssa_osc0 vssa_osc0 GND
AC14 vssa_osc1 vssa_osc1 GND
AD13, AE13 vssa_pcie vssa_pcie GND
AE10 vssa_sata vssa_sata GND
AA11, AB11 vssa_usb vssa_usb GND
AD10 vssa_usb3 vssa_usb3 GND
U14 vssa_video vssa_video GND
AD17 Wakeup0 Wakeup0 0 I OFF OFF 15 1.8/3.3 vddshv5 Yes IHHV1833 PU/PD
dcan1_rx 1 I 1
gpio1_0 14 I
Driver off 15 I
AC17 Wakeup1 Wakeup1 0 I OFF OFF 15 1.8/3.3 vddshv5 Yes IHHV1833 PU/PD
dcan2_rx 1 I 1
gpio1_1 14 I
Driver off 15 I
AB16 Wakeup2 Wakeup2 0 I OFF OFF 15 1.8/3.3 vddshv5 Yes IHHV1833 PU/PD
sys_nirq2 1 I
gpio1_2 14 I
Driver off 15 I
AC16 Wakeup3 Wakeup3 0 I OFF OFF 15 1.8/3.3 vddshv5 Yes IHHV1833 PU/PD
sys_nirq1 1 I
gpio1_3 14 I
Driver off 15 I
AE15 xi_osc0 xi_osc0 0 I 1.8 vdda_osc No LVCMOS Analog
AC15 xi_osc1 xi_osc1 0 I 1.8 vdda_osc No LVCMOS Analog
AD15 xo_osc0 xo_osc0 0 O 1.8 vdda_osc No LVCMOS Analog
AC13 xo_osc1 xo_osc1 0 A 1.8 vdda_osc No LVCMOS Analog
D18 xref_clk0 xref_clk0 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp2_axr8 1 IO 0
mcasp1_axr4 2 IO 0
mcasp1_ahclkx 3 O
mcasp5_ahclkx 4 O
vin6a_d0 Yes / No 7 I 0
clkout2 9 O
timer13 10 IO
gpio6_17 14 IO
Driver off 15 I
E17 xref_clk1 xref_clk1 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp2_axr9 1 IO 0
mcasp1_axr5 2 IO 0
mcasp2_ahclkx 3 O
mcasp6_ahclkx 4 O
vin6a_clk0 Yes / No 7 I 0
timer14 10 IO
gpio6_18 14 IO
Driver off 15 I
B26 xref_clk2 xref_clk2 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp2_axr10 1 IO 0
mcasp1_axr6 2 IO 0
mcasp3_ahclkx 3 O
mcasp7_ahclkx 4 O
vout2_clk Yes / No 6 O
vin4a_clk0 Yes / No 8 I 0
timer15 10 IO
gpio6_19 14 IO
Driver off 15 I
C23 xref_clk3 xref_clk3 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp2_axr11 1 IO 0
mcasp1_axr7 2 IO 0
mcasp4_ahclkx 3 O
mcasp8_ahclkx 4 O
vout2_de Yes / No 6 O
vin4a_de0 Yes / No 8 I 0
clkout3 9 O
timer16 10 IO
gpio6_20 14 IO
Driver off 15 I
  1. NA in this table stands for Not Applicable.
  2. For more information on recommended operating conditions, see Table 5-4, Recommended Operating Conditions.
  3. The pullup or pulldown block strength is equal to: minimum = 50 μA, typical = 100 μA, maximum = 250 μA.
  4. The output impedance settings of this IO cell are programmable; by default, the value is DS[1:0] = 10, this means 40 Ω. For more information on DS[1:0] register configuration, see the Device TRM.
  5. IO drive strength for usb1_dp, usb1_dm, usb2_dp and usb2_dm: minimum 18.3 mA, maximum 89 mA (for a power supply vdda33v_usb1 and vdda33v_usb2 = 3.46 V).
  6. Minimum PU = 900 Ω, maximum PU = 3.090 kΩ and minimum PD = 14.25 kΩ, maximum PD = 24.8 kΩ.
    For more information, see chapter 7 of the USB2.0 specification, in particular section Signaling / Device Speed Identification.
  7. In PUx / PDy, x and y = 60 to 200 μA.
    The output impedance settings (or drive strengths) of this IO are programmable (34 Ω, 40 Ω, 48 Ω, 60 Ω, 80 Ω) depending on the values of the I[2:0] registers.
  8. The VOUT3 interface when multiplexed onto balls mapped to the VDDSHV6 supply rail is restricted to operating in 1.8V mode only (VDDSHV6 must be supplied with 1.8V). 3.3V mode is not supported. This must be considered in the pin mux programming and VDDSHVx supply connections.
  9. The internal pull resistors for balls K7, M7, J5, K6, J4, J6, H4, H5 are permanently disabled when sysboot15 is set to 1 as described in the section Sysboot Configuration of the Device TRM. If internal pull-up/down resistors are desired on these balls then sysboot15 should be set to 0. If gpmc boot mode is used with SYSBOOT15=1 (not recommended) then external pull-downs should be implemented to keep the address bus at logic-0 value during boot since the gpmc ms-address bits are high-z during boot.

4.3 Multiplexing Characteristics

Table 4-3 describes the device multiplexing (no characteristics are available in this table).

NOTE

This table doesn't take into account subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 4.4, Signal Descriptions.

NOTE

For more information, see the Control Module / Control Module Functional Description / PAD Functional Multiplexing and Configuration section of the Device TRM.

NOTE

Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration (Hi-Z mode is not an input signal).

NOTE

When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be avoided.

CAUTION

The I/O timings provided in Section 7Timing Requirements and Switching Characteristics are valid only if signals within a single IOSET are used. The IOSETs are defined in the corresponding tables.

Table 4-3 Multiplexing Characteristics(1)

ADDRESS REGISTER NAME BALL NUMBER MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
0 1 2 3 4 5 6 7 8 9 10 14 15
P25 ddr2_a6
Y23 ddr1_d26
Y19 ddr1_d21
AE15 xi_osc0
AH24 ddr1_nck
AG15 ljcb_clkp
AF24 ddr1_d4
U25 ddr2_wen
F27 ddr2_d5
V25 ddr1_ecc_d6
M27 ddr2_dqsn3
G26 ddr2_d12
AG19 hdmi1_data2x
AF21 ddr1_a4
E27 ddr2_d6
F24 ddr2_d3
H26 ddr2_d11
W23 ddr1_ecc_d3
Y27 ddr1_dqsn3
AC24 ddr1_d14
J24 ddr2_d15
R26 ddr2_a1
G27 ddr2_dqsn0
AF28 ddr1_d11
AA23 ddr1_d24
AD18 ddr1_a15
H23 ddr2_d8
AH16 hdmi1_clocky
AC20 ddr1_a2
AA24 ddr1_d27
W19 ddr1_ecc_d2
L24 ddr2_d20
AG11 pcie_rxn1
AG21 ddr1_rst
AE28 ddr1_dqsn1
AC11 usb_txn0
L22 ddr2_d16
U28 ddr2_casn
K22 ddr2_d22
AG25 ddr1_dqsn0
W20 ddr1_d17
AF14 rtc_iso
AA27 ddr1_dqm3
AF25 ddr1_d0
AF23 ddr1_d6
AG18 hdmi1_data1x
AG10 sata1_txn0
AF20 ddr1_rasn
V26 ddr1_dqm_ecc
V20 ddr1_d16
G25 ddr2_d1
AH13 pcie_rxp0
AC18 ddr1_casn
AG9 sata1_rxp0
AH23 ddr1_csn0
AE11 usb2_dp
R25 ddr2_a0
Y24 ddr1_d28
AH15 ljcb_clkn
AD20 ddr1_a0
AA25 ddr1_d30
L23 ddr2_d19
AD14 rtc_osc_xo
J25 ddr2_d13
AC25 ddr1_d13
AB23 ddr1_dqm1
U22 ddr2_a15
T22 ddr2_a13
AH19 hdmi1_data2y
M26 ddr2_d31
AB27 ddr1_d22
AG14 pcie_txn0
Y28 ddr1_dqs3
J20 ddr2_d23
AB19 ddr1_a3
AH10 sata1_txp0
G28 ddr2_dqs0
AG24 ddr1_ck
AE24 ddr1_d5
AC15 xi_osc1
AC21 ddr1_a12
K28 ddr2_dqsn2
AF12 usb_rxn0
L28 ddr2_d27
M24 ddr2_d29
AH9 sata1_rxn0
AC26 ddr1_dqm2
AA28 ddr1_d31
H28 ddr2_dqsn1
AD23 ddr1_dqm0
E26 ddr2_d0
AE27 ddr1_dqs1
AF27 ddr1_d9
V24 ddr1_ecc_d5
K23 ddr2_dqm2
K20 ddr2_d17
T28 ddr2_ck
H24 ddr2_d10
AG27 ddr1_d10
R23 ddr2_odt0
U27 ddr2_ba1
AF22 ddr1_a8
U23 ddr2_ba0
AH21 ddr1_wen
AE21 ddr1_a7
AC12 usb1_dm
AH12 pcie_txp1
Y20 ddr1_d23
AC27 ddr1_d20
AE23 ddr1_d7
T27 ddr2_nck
AG22 ddr1_cke
AD27 ddr1_dqs2
AH14 pcie_txp0
AH26 ddr1_d3
AD21 ddr1_a10
N28 ddr2_a12
Y25 ddr1_ecc_d4
AE17 ddr1_a14
AH18 hdmi1_data1y
AH22 ddr1_a5
J26 ddr2_d14
W22 ddr1_ecc_d0
V23 ddr1_ecc_d1
AE12 usb_rxp0
AE14 rtc_osc_xi_clkin32
AH11 pcie_rxp1
AG23 ddr1_a6
H27 ddr2_dqs1
AB18 ddr1_ba2
AG17 hdmi1_data0x
AF26 ddr1_d1
H25 ddr2_d9
M25 ddr2_d30
AD11 usb_txp0
L27 ddr2_d24
V27 ddr1_dqs_ecc
AF17 ddr1_ba0
AE26 ddr1_d12
G24 ddr2_dqm1
K27 ddr2_dqs2
AC19 ddr1_a1
AG13 pcie_rxn0
L26 ddr2_d25
AB28 ddr1_d18
N23 ddr2_a10
M22 ddr2_dqm3
U26 ddr2_ba2
Y26 ddr1_ecc_d7
P24 ddr2_csn0
R22 ddr2_a14
AD22 ddr1_a11
N20 ddr2_a7
M23 ddr2_d28
AD28 ddr1_dqsn2
U24 ddr2_cke
P22 ddr2_a5
AE18 ddr1_ba1
F26 ddr2_d4
AE20 ddr1_odt0
N22 ddr2_vref0
E28 ddr2_d7
F25 ddr2_d2
AF11 usb2_dm
R24 ddr2_rst
AD15 xo_osc0
R27 ddr2_a3
AE22 ddr1_a9
Y18 ddr1_vref0
AC13 xo_osc1
F28 ddr2_dqm0
J23 ddr2_d21
P26 ddr2_a11
M28 ddr2_dqs3
AD12 usb1_dp
Y22 ddr1_d25
T23 ddr2_rasn
AH17 hdmi1_data0y
N27 ddr2_a9
P23 ddr2_a4
AG26 ddr1_d2
AH25 ddr1_dqs0
AG12 pcie_txn1
AF18 ddr1_a13
K21 ddr2_d18
AC28 ddr1_d19
V28 ddr1_dqsn_ecc
P27 ddr2_a8
AC23 ddr1_d8
F22 porz
L25 ddr2_d26
AG16 hdmi1_clockx
R28 ddr2_a2
AA26 ddr1_d29
AD25 ddr1_d15
0x1400 CTRL_CORE_PAD_GPMC_AD0 M6 gpmc_ad0 vin3a_d0 vout3_d0 gpio1_6 sysboot0
0x1404 CTRL_CORE_PAD_GPMC_AD1 M2 gpmc_ad1 vin3a_d1 vout3_d1 gpio1_7 sysboot1
0x1408 CTRL_CORE_PAD_GPMC_AD2 L5 gpmc_ad2 vin3a_d2 vout3_d2 gpio1_8 sysboot2
0x140C CTRL_CORE_PAD_GPMC_AD3 M1 gpmc_ad3 vin3a_d3 vout3_d3 gpio1_9 sysboot3
0x1410 CTRL_CORE_PAD_GPMC_AD4 L6 gpmc_ad4 vin3a_d4 vout3_d4 gpio1_10 sysboot4
0x1414 CTRL_CORE_PAD_GPMC_AD5 L4 gpmc_ad5 vin3a_d5 vout3_d5 gpio1_11 sysboot5
0x1418 CTRL_CORE_PAD_GPMC_AD6 L3 gpmc_ad6 vin3a_d6 vout3_d6 gpio1_12 sysboot6
0x141C CTRL_CORE_PAD_GPMC_AD7 L2 gpmc_ad7 vin3a_d7 vout3_d7 gpio1_13 sysboot7
0x1420 CTRL_CORE_PAD_GPMC_AD8 L1 gpmc_ad8 vin3a_d8 vout3_d8 gpio7_18 sysboot8
0x1424 CTRL_CORE_PAD_GPMC_AD9 K2 gpmc_ad9 vin3a_d9 vout3_d9 gpio7_19 sysboot9
0x1428 CTRL_CORE_PAD_GPMC_AD10 J1 gpmc_ad10 vin3a_d10 vout3_d10 gpio7_28 sysboot10
0x142C CTRL_CORE_PAD_GPMC_AD11 J2 gpmc_ad11 vin3a_d11 vout3_d11 gpio7_29 sysboot11
0x1430 CTRL_CORE_PAD_GPMC_AD12 H1 gpmc_ad12 vin3a_d12 vout3_d12 gpio1_18 sysboot12
0x1434 CTRL_CORE_PAD_GPMC_AD13 J3 gpmc_ad13 vin3a_d13 vout3_d13 gpio1_19 sysboot13
0x1438 CTRL_CORE_PAD_GPMC_AD14 H2 gpmc_ad14 vin3a_d14 vout3_d14 gpio1_20 sysboot14
0x143C CTRL_CORE_PAD_GPMC_AD15 H3 gpmc_ad15 vin3a_d15 vout3_d15 gpio1_21 sysboot15
0x1440 CTRL_CORE_PAD_GPMC_A0 R6 gpmc_a0 vin3a_d16 vout3_d16 vin4a_d0 vin4b_d0 i2c4_scl uart5_rxd gpio7_3 Driver off
0x1444 CTRL_CORE_PAD_GPMC_A1 T9 gpmc_a1 vin3a_d17 vout3_d17 vin4a_d1 vin4b_d1 i2c4_sda uart5_txd gpio7_4 Driver off
0x1448 CTRL_CORE_PAD_GPMC_A2 T6 gpmc_a2 vin3a_d18 vout3_d18 vin4a_d2 vin4b_d2 uart7_rxd uart5_ctsn gpio7_5 Driver off
0x144C CTRL_CORE_PAD_GPMC_A3 T7 gpmc_a3 qspi1_cs2 vin3a_d19 vout3_d19 vin4a_d3 vin4b_d3 uart7_txd uart5_rtsn gpio7_6 Driver off
0x1450 CTRL_CORE_PAD_GPMC_A4 P6 gpmc_a4 qspi1_cs3 vin3a_d20 vout3_d20 vin4a_d4 vin4b_d4 i2c5_scl uart6_rxd gpio1_26 Driver off
0x1454 CTRL_CORE_PAD_GPMC_A5 R9 gpmc_a5 vin3a_d21 vout3_d21 vin4a_d5 vin4b_d5 i2c5_sda uart6_txd gpio1_27 Driver off
0x1458 CTRL_CORE_PAD_GPMC_A6 R5 gpmc_a6 vin3a_d22 vout3_d22 vin4a_d6 vin4b_d6 uart8_rxd uart6_ctsn gpio1_28 Driver off
0x145C CTRL_CORE_PAD_GPMC_A7 P5 gpmc_a7 vin3a_d23 vout3_d23 vin4a_d7 vin4b_d7 uart8_txd uart6_rtsn gpio1_29 Driver off
0x1460 CTRL_CORE_PAD_GPMC_A8 N7 gpmc_a8 vin3a_hsync0 vout3_hsync vin4b_hsync1 timer12 spi4_sclk gpio1_30 Driver off
0x1464 CTRL_CORE_PAD_GPMC_A9 R4 gpmc_a9 vin3a_vsync0 vout3_vsync vin4b_vsync1 timer11 spi4_d1 gpio1_31 Driver off
0x1468 CTRL_CORE_PAD_GPMC_A10 N9 gpmc_a10 vin3a_de0 vout3_de vin4b_clk1 timer10 spi4_d0 gpio2_0 Driver off
0x146C CTRL_CORE_PAD_GPMC_A11 P9 gpmc_a11 vin3a_fld0 vout3_fld vin4a_fld0 vin4b_de1 timer9 spi4_cs0 gpio2_1 Driver off
0x1470 CTRL_CORE_PAD_GPMC_A12 P4 gpmc_a12 vin4a_clk0 gpmc_a0 vin4b_fld1 timer8 spi4_cs1 dma_evt1 gpio2_2 Driver off
0x1474 CTRL_CORE_PAD_GPMC_A13 R3 gpmc_a13 qspi1_rtclk vin4a_hsync0 timer7 spi4_cs2 dma_evt2 gpio2_3 Driver off
0x1478 CTRL_CORE_PAD_GPMC_A14 T2 gpmc_a14 qspi1_d3 vin4a_vsync0 timer6 spi4_cs3 gpio2_4 Driver off
0x147C CTRL_CORE_PAD_GPMC_A15 U2 gpmc_a15 qspi1_d2 vin4a_d8 timer5 gpio2_5 Driver off
0x1480 CTRL_CORE_PAD_GPMC_A16 U1 gpmc_a16 qspi1_d0 vin4a_d9 gpio2_6 Driver off
0x1484 CTRL_CORE_PAD_GPMC_A17 P3 gpmc_a17 qspi1_d1 vin4a_d10 gpio2_7 Driver off
0x1488 CTRL_CORE_PAD_GPMC_A18 R2 gpmc_a18 qspi1_sclk vin4a_d11 gpio2_8 Driver off
0x148C CTRL_CORE_PAD_GPMC_A19 K7 gpmc_a19 mmc2_dat4 gpmc_a13 vin4a_d12 vin3b_d0 gpio2_9 Driver off
0x1490 CTRL_CORE_PAD_GPMC_A20 M7 gpmc_a20 mmc2_dat5 gpmc_a14 vin4a_d13 vin3b_d1 gpio2_10 Driver off
0x1494 CTRL_CORE_PAD_GPMC_A21 J5 gpmc_a21 mmc2_dat6 gpmc_a15 vin4a_d14 vin3b_d2 gpio2_11 Driver off
0x1498 CTRL_CORE_PAD_GPMC_A22 K6 gpmc_a22 mmc2_dat7 gpmc_a16 vin4a_d15 vin3b_d3 gpio2_12 Driver off
0x149C CTRL_CORE_PAD_GPMC_A23 J7 gpmc_a23 mmc2_clk gpmc_a17 vin4a_fld0 vin3b_d4 gpio2_13 Driver off
0x14A0 CTRL_CORE_PAD_GPMC_A24 J4 gpmc_a24 mmc2_dat0 gpmc_a18 vin3b_d5 gpio2_14 Driver off
0x14A4 CTRL_CORE_PAD_GPMC_A25 J6 gpmc_a25 mmc2_dat1 gpmc_a19 vin3b_d6 gpio2_15 Driver off
0x14A8 CTRL_CORE_PAD_GPMC_A26 H4 gpmc_a26 mmc2_dat2 gpmc_a20 vin3b_d7 gpio2_16 Driver off
0x14AC CTRL_CORE_PAD_GPMC_A27 H5 gpmc_a27 mmc2_dat3 gpmc_a21 vin3b_hsync1 gpio2_17 Driver off
0x14B0 CTRL_CORE_PAD_GPMC_CS1 H6 gpmc_cs1 mmc2_cmd gpmc_a22 vin4a_de0 vin3b_vsync1 gpio2_18 Driver off
0x14B4 CTRL_CORE_PAD_GPMC_CS0 T1 gpmc_cs0 gpio2_19 Driver off
0x14B8 CTRL_CORE_PAD_GPMC_CS2 P2 gpmc_cs2 qspi1_cs0 gpio2_20 Driver off
0x14BC CTRL_CORE_PAD_GPMC_CS3 P1 gpmc_cs3 qspi1_cs1 vin3a_clk0 vout3_clk gpmc_a1 gpio2_21 Driver off
0x14C0 CTRL_CORE_PAD_GPMC_CLK P7 gpmc_clk gpmc_cs7 clkout1 gpmc_wait1 vin4a_hsync0 vin4a_de0 vin3b_clk1 timer4 i2c3_scl dma_evt1 gpio2_22 Driver off
0x14C4 CTRL_CORE_PAD_GPMC_ADVN_ALE N1 gpmc_advn_ale gpmc_cs6 clkout2 gpmc_wait1 vin4a_vsync0 gpmc_a2 gpmc_a23 timer3 i2c3_sda dma_evt2 gpio2_23 Driver off
0x14C8 CTRL_CORE_PAD_GPMC_OEN_REN M5 gpmc_oen_ren gpio2_24 Driver off
0x14CC CTRL_CORE_PAD_GPMC_WEN M3 gpmc_wen gpio2_25 Driver off
0x14D0 CTRL_CORE_PAD_GPMC_BEN0 N6 gpmc_ben0 gpmc_cs4 vin1b_hsync1 vin3b_de1 timer2 dma_evt3 gpio2_26 Driver off
0x14D4 CTRL_CORE_PAD_GPMC_BEN1 M4 gpmc_ben1 gpmc_cs5 vin1b_de1 vin3b_clk1 gpmc_a3 vin3b_fld1 timer1 dma_evt4 gpio2_27 Driver off
0x14D8 CTRL_CORE_PAD_GPMC_WAIT0 N2 gpmc_wait0 gpio2_28 Driver off
0x14DC CTRL_CORE_PAD_VIN1A_CLK0 AG8 vin1a_clk0 vout3_d16 vout3_fld gpio2_30 Driver off
0x14E0 CTRL_CORE_PAD_VIN1B_CLK1 AH7 vin1b_clk1 vin3a_clk0 gpio2_31 Driver off
0x14E4 CTRL_CORE_PAD_VIN1A_DE0 AD9 vin1a_de0 vin1b_hsync1 vout3_d17 vout3_de uart7_rxd timer16 spi3_sclk eQEP1A_in gpio3_0 Driver off
0x14E8 CTRL_CORE_PAD_VIN1A_FLD0 AF9 vin1a_fld0 vin1b_vsync1 vout3_clk uart7_txd timer15 spi3_d1 eQEP1B_in gpio3_1 Driver off
0x14EC CTRL_CORE_PAD_VIN1A_HSYNC0 AE9 vin1a_hsync0 vin1b_fld1 vout3_hsync uart7_ctsn timer14 spi3_d0 eQEP1_index gpio3_2 Driver off
0x14F0 CTRL_CORE_PAD_VIN1A_VSYNC0 AF8 vin1a_vsync0 vin1b_de1 vout3_vsync uart7_rtsn timer13 spi3_cs0 eQEP1_strobe gpio3_3 Driver off
0x14F4 CTRL_CORE_PAD_VIN1A_D0 AE8 vin1a_d0 vout3_d7 vout3_d23 uart8_rxd ehrpwm1A gpio3_4 Driver off
0x14F8 CTRL_CORE_PAD_VIN1A_D1 AD8 vin1a_d1 vout3_d6 vout3_d22 uart8_txd ehrpwm1B gpio3_5 Driver off
0x14FC CTRL_CORE_PAD_VIN1A_D2 AG7 vin1a_d2 vout3_d5 vout3_d21 uart8_ctsn ehrpwm1_tripzone_input gpio3_6 Driver off
0x1500 CTRL_CORE_PAD_VIN1A_D3 AH6 vin1a_d3 vout3_d4 vout3_d20 uart8_rtsn eCAP1_in_PWM1_out gpio3_7 Driver off
0x1504 CTRL_CORE_PAD_VIN1A_D4 AH3 vin1a_d4 vout3_d3 vout3_d19 ehrpwm1_synci gpio3_8 Driver off
0x1508 CTRL_CORE_PAD_VIN1A_D5 AH5 vin1a_d5 vout3_d2 vout3_d18 ehrpwm1_synco gpio3_9 Driver off
0x150C CTRL_CORE_PAD_VIN1A_D6 AG6 vin1a_d6 vout3_d1 vout3_d17 eQEP2A_in gpio3_10 Driver off
0x1510 CTRL_CORE_PAD_VIN1A_D7 AH4 vin1a_d7 vout3_d0 vout3_d16 eQEP2B_in gpio3_11 Driver off
0x1514 CTRL_CORE_PAD_VIN1A_D8 AG4 vin1a_d8 vin1b_d7 vout3_d15 eQEP2_index gpio3_12 Driver off
0x1518 CTRL_CORE_PAD_VIN1A_D9 AG2 vin1a_d9 vin1b_d6 vout3_d14 eQEP2_strobe gpio3_13 Driver off
0x151C CTRL_CORE_PAD_VIN1A_D10 AG3 vin1a_d10 vin1b_d5 vout3_d13 gpio3_14 Driver off
0x1520 CTRL_CORE_PAD_VIN1A_D11 AG5 vin1a_d11 vin1b_d4 vout3_d12 gpmc_a23 gpio3_15 Driver off
0x1524 CTRL_CORE_PAD_VIN1A_D12 AF2 vin1a_d12 vin1b_d3 usb3_ulpi_d7 vout3_d11 gpmc_a24 gpio3_16 Driver off
0x1528 CTRL_CORE_PAD_VIN1A_D13 AF6 vin1a_d13 vin1b_d2 usb3_ulpi_d6 vout3_d10 gpmc_a25 gpio3_17 Driver off
0x152C CTRL_CORE_PAD_VIN1A_D14 AF3 vin1a_d14 vin1b_d1 usb3_ulpi_d5 vout3_d9 gpmc_a26 gpio3_18 Driver off
0x1530 CTRL_CORE_PAD_VIN1A_D15 AF4 vin1a_d15 vin1b_d0 usb3_ulpi_d4 vout3_d8 gpmc_a27 gpio3_19 Driver off
0x1534 CTRL_CORE_PAD_VIN1A_D16 AF1 vin1a_d16 vin1b_d7 usb3_ulpi_d3 vout3_d7 vin3a_d0 gpio3_20 Driver off
0x1538 CTRL_CORE_PAD_VIN1A_D17 AE3 vin1a_d17 vin1b_d6 usb3_ulpi_d2 vout3_d6 vin3a_d1 gpio3_21 Driver off
0x153C CTRL_CORE_PAD_VIN1A_D18 AE5 vin1a_d18 vin1b_d5 usb3_ulpi_d1 vout3_d5 vin3a_d2 gpio3_22 Driver off
0x1540 CTRL_CORE_PAD_VIN1A_D19 AE1 vin1a_d19 vin1b_d4 usb3_ulpi_d0 vout3_d4 vin3a_d3 gpio3_23 Driver off
0x1544 CTRL_CORE_PAD_VIN1A_D20 AE2 vin1a_d20 vin1b_d3 usb3_ulpi_nxt vout3_d3 vin3a_d4 gpio3_24 Driver off
0x1548 CTRL_CORE_PAD_VIN1A_D21 AE6 vin1a_d21 vin1b_d2 usb3_ulpi_dir vout3_d2 vin3a_d5 gpio3_25 Driver off
0x154C CTRL_CORE_PAD_VIN1A_D22 AD2 vin1a_d22 vin1b_d1 usb3_ulpi_stp vout3_d1 vin3a_d6 gpio3_26 Driver off
0x1550 CTRL_CORE_PAD_VIN1A_D23 AD3 vin1a_d23 vin1b_d0 usb3_ulpi_clk vout3_d0 vin3a_d7 gpio3_27 Driver off
0x1554 CTRL_CORE_PAD_VIN2A_CLK0 E1 vin2a_clk0 vout2_fld emu5 eQEP1A_in gpio3_28 Driver off
0x1558 CTRL_CORE_PAD_VIN2A_DE0 G2 vin2a_de0 vin2a_fld0 vin2b_fld1 vin2b_de1 vout2_de emu6 eQEP1B_in gpio3_29 Driver off
0x155C CTRL_CORE_PAD_VIN2A_FLD0 H7 vin2a_fld0 vin2b_clk1 vout2_clk emu7 eQEP1_index gpio3_30 Driver off
0x1560 CTRL_CORE_PAD_VIN2A_HSYNC0 G1 vin2a_hsync0 vin2b_hsync1 vout2_hsync emu8 uart9_rxd spi4_sclk eQEP1_strobe gpio3_31 Driver off
0x1564 CTRL_CORE_PAD_VIN2A_VSYNC0 G6 vin2a_vsync0 vin2b_vsync1 vout2_vsync emu9 uart9_txd spi4_d1 ehrpwm1A gpio4_0 Driver off
0x1568 CTRL_CORE_PAD_VIN2A_D0 F2 vin2a_d0 vout2_d23 emu10 uart9_ctsn spi4_d0 ehrpwm1B gpio4_1 Driver off
0x156C CTRL_CORE_PAD_VIN2A_D1 F3 vin2a_d1 vout2_d22 emu11 uart9_rtsn spi4_cs0 ehrpwm1_tripzone_input gpio4_2 Driver off
0x1570 CTRL_CORE_PAD_VIN2A_D2 D1 vin2a_d2 vout2_d21 emu12 uart10_rxd eCAP1_in_PWM1_out gpio4_3 Driver off
0x1574 CTRL_CORE_PAD_VIN2A_D3 E2 vin2a_d3 vout2_d20 emu13 uart10_txd ehrpwm1_synci gpio4_4 Driver off
0x1578 CTRL_CORE_PAD_VIN2A_D4 D2 vin2a_d4 vout2_d19 emu14 uart10_ctsn ehrpwm1_synco gpio4_5 Driver off
0x157C CTRL_CORE_PAD_VIN2A_D5 F4 vin2a_d5 vout2_d18 emu15 uart10_rtsn eQEP2A_in gpio4_6 Driver off
0x1580 CTRL_CORE_PAD_VIN2A_D6 C1 vin2a_d6 vout2_d17 emu16 mii1_rxd1 eQEP2B_in gpio4_7 Driver off
0x1584 CTRL_CORE_PAD_VIN2A_D7 E4 vin2a_d7 vout2_d16 emu17 mii1_rxd2 eQEP2_index gpio4_8 Driver off
0x1588 CTRL_CORE_PAD_VIN2A_D8 F5 vin2a_d8 vout2_d15 emu18 mii1_rxd3 eQEP2_strobe gpio4_9 Driver off
0x158C CTRL_CORE_PAD_VIN2A_D9 E6 vin2a_d9 vout2_d14 emu19 mii1_rxd0 ehrpwm2A gpio4_10 Driver off
0x1590 CTRL_CORE_PAD_VIN2A_D10 D3 vin2a_d10 mdio_mclk vout2_d13 ehrpwm2B gpio4_11 Driver off
0x1594 CTRL_CORE_PAD_VIN2A_D11 F6 vin2a_d11 mdio_d vout2_d12 ehrpwm2_tripzone_input gpio4_12 Driver off
0x1598 CTRL_CORE_PAD_VIN2A_D12 D5 vin2a_d12 rgmii1_txc vout2_d11 mii1_rxclk eCAP2_in_PWM2_out gpio4_13 Driver off
0x159C CTRL_CORE_PAD_VIN2A_D13 C2 vin2a_d13 rgmii1_txctl vout2_d10 mii1_rxdv eQEP3A_in gpio4_14 Driver off
0x15A0 CTRL_CORE_PAD_VIN2A_D14 C3 vin2a_d14 rgmii1_txd3 vout2_d9 mii1_txclk eQEP3B_in gpio4_15 Driver off
0x15A4 CTRL_CORE_PAD_VIN2A_D15 C4 vin2a_d15 rgmii1_txd2 vout2_d8 mii1_txd0 eQEP3_index gpio4_16 Driver off
0x15A8 CTRL_CORE_PAD_VIN2A_D16 B2 vin2a_d16 vin2b_d7 rgmii1_txd1 vout2_d7 vin3a_d8 mii1_txd1 eQEP3_strobe gpio4_24 Driver off
0x15AC CTRL_CORE_PAD_VIN2A_D17 D6 vin2a_d17 vin2b_d6 rgmii1_txd0 vout2_d6 vin3a_d9 mii1_txd2 ehrpwm3A gpio4_25 Driver off
0x15B0 CTRL_CORE_PAD_VIN2A_D18 C5 vin2a_d18 vin2b_d5 rgmii1_rxc vout2_d5 vin3a_d10 mii1_txd3 ehrpwm3B gpio4_26 Driver off
0x15B4 CTRL_CORE_PAD_VIN2A_D19 A3 vin2a_d19 vin2b_d4 rgmii1_rxctl vout2_d4 vin3a_d11 mii1_txer ehrpwm3_tripzone_input gpio4_27 Driver off
0x15B8 CTRL_CORE_PAD_VIN2A_D20 B3 vin2a_d20 vin2b_d3 rgmii1_rxd3 vout2_d3 vin3a_de0 vin3a_d12 mii1_rxer eCAP3_in_PWM3_out gpio4_28 Driver off
0x15BC CTRL_CORE_PAD_VIN2A_D21 B4 vin2a_d21 vin2b_d2 rgmii1_rxd2 vout2_d2 vin3a_fld0 vin3a_d13 mii1_col gpio4_29 Driver off
0x15C0 CTRL_CORE_PAD_VIN2A_D22 B5 vin2a_d22 vin2b_d1 rgmii1_rxd1 vout2_d1 vin3a_hsync0 vin3a_d14 mii1_crs gpio4_30 Driver off
0x15C4 CTRL_CORE_PAD_VIN2A_D23 A4 vin2a_d23 vin2b_d0 rgmii1_rxd0 vout2_d0 vin3a_vsync0 vin3a_d15 mii1_txen gpio4_31 Driver off
0x15C8 CTRL_CORE_PAD_VOUT1_CLK D11 vout1_clk vin4a_fld0 vin3a_fld0 spi3_cs0 gpio4_19 Driver off
0x15CC CTRL_CORE_PAD_VOUT1_DE B10 vout1_de vin4a_de0 vin3a_de0 spi3_d1 gpio4_20 Driver off
0x15D0 CTRL_CORE_PAD_VOUT1_FLD B11 vout1_fld vin4a_clk0 vin3a_clk0 spi3_cs1 gpio4_21 Driver off
0x15D4 CTRL_CORE_PAD_VOUT1_HSYNC C11 vout1_hsync vin4a_hsync0 vin3a_hsync0 spi3_d0 gpio4_22 Driver off
0x15D8 CTRL_CORE_PAD_VOUT1_VSYNC E11 vout1_vsync vin4a_vsync0 vin3a_vsync0 spi3_sclk gpio4_23 Driver off
0x15DC CTRL_CORE_PAD_VOUT1_D0 F11 vout1_d0 uart5_rxd vin4a_d16 vin3a_d16 spi3_cs2 gpio8_0 Driver off
0x15E0 CTRL_CORE_PAD_VOUT1_D1 G10 vout1_d1 uart5_txd vin4a_d17 vin3a_d17 gpio8_1 Driver off
0x15E4 CTRL_CORE_PAD_VOUT1_D2 F10 vout1_d2 emu2 vin4a_d18 vin3a_d18 obs0 obs16 obs_irq1 gpio8_2 Driver off
0x15E8 CTRL_CORE_PAD_VOUT1_D3 G11 vout1_d3 emu5 vin4a_d19 vin3a_d19 obs1 obs17 obs_dmarq1 gpio8_3 Driver off
0x15EC CTRL_CORE_PAD_VOUT1_D4 E9 vout1_d4 emu6 vin4a_d20 vin3a_d20 obs2 obs18 gpio8_4 Driver off
0x15F0 CTRL_CORE_PAD_VOUT1_D5 F9 vout1_d5 emu7 vin4a_d21 vin3a_d21 obs3 obs19 gpio8_5 Driver off
0x15F4 CTRL_CORE_PAD_VOUT1_D6 F8 vout1_d6 emu8 vin4a_d22 vin3a_d22 obs4 obs20 gpio8_6 Driver off
0x15F8 CTRL_CORE_PAD_VOUT1_D7 E7 vout1_d7 emu9 vin4a_d23 vin3a_d23 gpio8_7 Driver off
0x15FC CTRL_CORE_PAD_VOUT1_D8 E8 vout1_d8 uart6_rxd vin4a_d8 vin3a_d8 gpio8_8 Driver off
0x1600 CTRL_CORE_PAD_VOUT1_D9 D9 vout1_d9 uart6_txd vin4a_d9 vin3a_d9 gpio8_9 Driver off
0x1604 CTRL_CORE_PAD_VOUT1_D10 D7 vout1_d10 emu3 vin4a_d10 vin3a_d10 obs5 obs21 obs_irq2 gpio8_10 Driver off
0x1608 CTRL_CORE_PAD_VOUT1_D11 D8 vout1_d11 emu10 vin4a_d11 vin3a_d11 obs6 obs22 obs_dmarq2 gpio8_11 Driver off
0x160C CTRL_CORE_PAD_VOUT1_D12 A5 vout1_d12 emu11 vin4a_d12 vin3a_d12 obs7 obs23 gpio8_12 Driver off
0x1610 CTRL_CORE_PAD_VOUT1_D13 C6 vout1_d13 emu12 vin4a_d13 vin3a_d13 obs8 obs24 gpio8_13 Driver off
0x1614 CTRL_CORE_PAD_VOUT1_D14 C8 vout1_d14 emu13 vin4a_d14 vin3a_d14 obs9 obs25 gpio8_14 Driver off
0x1618 CTRL_CORE_PAD_VOUT1_D15 C7 vout1_d15 emu14 vin4a_d15 vin3a_d15 obs10 obs26 gpio8_15 Driver off
0x161C CTRL_CORE_PAD_VOUT1_D16 B7 vout1_d16 uart7_rxd vin4a_d0 vin3a_d0 gpio8_16 Driver off
0x1620 CTRL_CORE_PAD_VOUT1_D17 B8 vout1_d17 uart7_txd vin4a_d1 vin3a_d1 gpio8_17 Driver off
0x1624 CTRL_CORE_PAD_VOUT1_D18 A7 vout1_d18 emu4 vin4a_d2 vin3a_d2 obs11 obs27 gpio8_18 Driver off
0x1628 CTRL_CORE_PAD_VOUT1_D19 A8 vout1_d19 emu15 vin4a_d3 vin3a_d3 obs12 obs28 gpio8_19 Driver off
0x162C CTRL_CORE_PAD_VOUT1_D20 C9 vout1_d20 emu16 vin4a_d4 vin3a_d4 obs13 obs29 gpio8_20 Driver off
0x1630 CTRL_CORE_PAD_VOUT1_D21 A9 vout1_d21 emu17 vin4a_d5 vin3a_d5 obs14 obs30 gpio8_21 Driver off
0x1634 CTRL_CORE_PAD_VOUT1_D22 B9 vout1_d22 emu18 vin4a_d6 vin3a_d6 obs15 obs31 gpio8_22 Driver off
0x1638 CTRL_CORE_PAD_VOUT1_D23 A10 vout1_d23 emu19 vin4a_d7 vin3a_d7 spi3_cs3 gpio8_23 Driver off
0x163C CTRL_CORE_PAD_MDIO_MCLK V1 mdio_mclk uart3_rtsn mii0_col vin2a_clk0 vin4b_clk1 gpio5_15 Driver off
0x1640 CTRL_CORE_PAD_MDIO_D U4 mdio_d uart3_ctsn mii0_txer vin2a_d0 vin4b_d0 gpio5_16 Driver off
0x1644 CTRL_CORE_PAD_RMII_MHZ_50_CLK U3 RMII_MHZ_50_CLK vin2a_d11 gpio5_17 Driver off
0x1648 CTRL_CORE_PAD_UART3_RXD V2 uart3_rxd rmii1_crs mii0_rxdv vin2a_d1 vin4b_d1 spi3_sclk gpio5_18 Driver off
0x164C CTRL_CORE_PAD_UART3_TXD Y1 uart3_txd rmii1_rxer mii0_rxclk vin2a_d2 vin4b_d2 spi3_d1 spi4_cs1 gpio5_19 Driver off
0x1650 CTRL_CORE_PAD_RGMII0_TXC W9 rgmii0_txc uart3_ctsn rmii1_rxd1 mii0_rxd3 vin2a_d3 vin4b_d3 usb4_ulpi_clk spi3_d0 spi4_cs2 gpio5_20 Driver off
0x1654 CTRL_CORE_PAD_RGMII0_TXCTL V9 rgmii0_txctl uart3_rtsn rmii1_rxd0 mii0_rxd2 vin2a_d4 vin4b_d4 usb4_ulpi_stp spi3_cs0 spi4_cs3 gpio5_21 Driver off
0x1658 CTRL_CORE_PAD_RGMII0_TXD3 V7 rgmii0_txd3 rmii0_crs mii0_crs vin2a_de0 vin4b_de1 usb4_ulpi_dir spi4_sclk uart4_rxd gpio5_22 Driver off
0x165C CTRL_CORE_PAD_RGMII0_TXD2 U7 rgmii0_txd2 rmii0_rxer mii0_rxer vin2a_hsync0 vin4b_hsync1 usb4_ulpi_nxt spi4_d1 uart4_txd gpio5_23 Driver off
0x1660 CTRL_CORE_PAD_RGMII0_TXD1 V6 rgmii0_txd1 rmii0_rxd1 mii0_rxd1 vin2a_vsync0 vin4b_vsync1 usb4_ulpi_d0 spi4_d0 uart4_ctsn gpio5_24 Driver off
0x1664 CTRL_CORE_PAD_RGMII0_TXD0 U6 rgmii0_txd0 rmii0_rxd0 mii0_rxd0 vin2a_d10 usb4_ulpi_d1 spi4_cs0 uart4_rtsn gpio5_25 Driver off
0x1668 CTRL_CORE_PAD_RGMII0_RXC U5 rgmii0_rxc rmii1_txen mii0_txclk vin2a_d5 vin4b_d5 usb4_ulpi_d2 gpio5_26 Driver off
0x166C CTRL_CORE_PAD_RGMII0_RXCTL V5 rgmii0_rxctl rmii1_txd1 mii0_txd3 vin2a_d6 vin4b_d6 usb4_ulpi_d3 gpio5_27 Driver off
0x1670 CTRL_CORE_PAD_RGMII0_RXD3 V4 rgmii0_rxd3 rmii1_txd0 mii0_txd2 vin2a_d7 vin4b_d7 usb4_ulpi_d4 gpio5_28 Driver off
0x1674 CTRL_CORE_PAD_RGMII0_RXD2 V3 rgmii0_rxd2 rmii0_txen mii0_txen vin2a_d8 usb4_ulpi_d5 gpio5_29 Driver off
0x1678 CTRL_CORE_PAD_RGMII0_RXD1 Y2 rgmii0_rxd1 rmii0_txd1 mii0_txd1 vin2a_d9 usb4_ulpi_d6 gpio5_30 Driver off
0x167C CTRL_CORE_PAD_RGMII0_RXD0 W2 rgmii0_rxd0 rmii0_txd0 mii0_txd0 vin2a_fld0 vin4b_fld1 usb4_ulpi_d7 gpio5_31 Driver off
0x1680 CTRL_CORE_PAD_USB1_DRVVBUS AB10 usb1_drvvbus timer16 gpio6_12 Driver off
0x1684 CTRL_CORE_PAD_USB2_DRVVBUS AC10 usb2_drvvbus timer15 gpio6_13 Driver off
0x1688 CTRL_CORE_PAD_GPIO6_14 E21 gpio6_14 mcasp1_axr8 dcan2_tx uart10_rxd vout2_hsync vin4a_hsync0 i2c3_sda timer1 gpio6_14 Driver off
0x168C CTRL_CORE_PAD_GPIO6_15 F20 gpio6_15 mcasp1_axr9 dcan2_rx uart10_txd vout2_vsync vin4a_vsync0 i2c3_scl timer2 gpio6_15 Driver off
0x1690 CTRL_CORE_PAD_GPIO6_16 F21 gpio6_16 mcasp1_axr10 vout2_fld vin4a_fld0 clkout1 timer3 gpio6_16 Driver off
0x1694 CTRL_CORE_PAD_XREF_CLK0 D18 xref_clk0 mcasp2_axr8 mcasp1_axr4 mcasp1_ahclkx mcasp5_ahclkx vin6a_d0 clkout2 timer13 gpio6_17 Driver off
0x1698 CTRL_CORE_PAD_XREF_CLK1 E17 xref_clk1 mcasp2_axr9 mcasp1_axr5 mcasp2_ahclkx mcasp6_ahclkx vin6a_clk0 timer14 gpio6_18 Driver off
0x169C CTRL_CORE_PAD_XREF_CLK2 B26 xref_clk2 mcasp2_axr10 mcasp1_axr6 mcasp3_ahclkx mcasp7_ahclkx vout2_clk vin4a_clk0 timer15 gpio6_19 Driver off
0x16A0 CTRL_CORE_PAD_XREF_CLK3 C23 xref_clk3 mcasp2_axr11 mcasp1_axr7 mcasp4_ahclkx mcasp8_ahclkx vout2_de vin4a_de0 clkout3 timer16 gpio6_20 Driver off
0x16A4 CTRL_CORE_PAD_MCASP1_ACLKX C14 mcasp1_aclkx vin6a_fld0 i2c3_sda gpio7_31 Driver off
0x16A8 CTRL_CORE_PAD_MCASP1_FSX D14 mcasp1_fsx vin6a_de0 i2c3_scl gpio7_30 Driver off
0x16AC CTRL_CORE_PAD_MCASP1_ACLKR B14 mcasp1_aclkr mcasp7_axr2 vout2_d0 vin4a_d0 i2c4_sda gpio5_0 Driver off
0x16B0 CTRL_CORE_PAD_MCASP1_FSR J14 mcasp1_fsr mcasp7_axr3 vout2_d1 vin4a_d1 i2c4_scl gpio5_1 Driver off
0x16B4 CTRL_CORE_PAD_MCASP1_AXR0 G12 mcasp1_axr0 uart6_rxd vin6a_vsync0 i2c5_sda gpio5_2 Driver off
0x16B8 CTRL_CORE_PAD_MCASP1_AXR1 F12 mcasp1_axr1 uart6_txd vin6a_hsync0 i2c5_scl gpio5_3 Driver off
0x16BC CTRL_CORE_PAD_MCASP1_AXR2 G13 mcasp1_axr2 mcasp6_axr2 uart6_ctsn vout2_d2 vin4a_d2 gpio5_4 Driver off
0x16C0 CTRL_CORE_PAD_MCASP1_AXR3 J11 mcasp1_axr3 mcasp6_axr3 uart6_rtsn vout2_d3 vin4a_d3 gpio5_5 Driver off
0x16C4 CTRL_CORE_PAD_MCASP1_AXR4 E12 mcasp1_axr4 mcasp4_axr2 vout2_d4 vin4a_d4 gpio5_6 Driver off
0x16C8 CTRL_CORE_PAD_MCASP1_AXR5 F13 mcasp1_axr5 mcasp4_axr3 vout2_d5 vin4a_d5 gpio5_7 Driver off
0x16CC CTRL_CORE_PAD_MCASP1_AXR6 C12 mcasp1_axr6 mcasp5_axr2 vout2_d6 vin4a_d6 gpio5_8 Driver off
0x16D0 CTRL_CORE_PAD_MCASP1_AXR7 D12 mcasp1_axr7 mcasp5_axr3 vout2_d7 vin4a_d7 timer4 gpio5_9 Driver off
0x16D4 CTRL_CORE_PAD_MCASP1_AXR8 B12 mcasp1_axr8 mcasp6_axr0 spi3_sclk vin6a_d15 timer5 gpio5_10 Driver off
0x16D8 CTRL_CORE_PAD_MCASP1_AXR9 A11 mcasp1_axr9 mcasp6_axr1 spi3_d1 vin6a_d14 timer6 gpio5_11 Driver off
0x16DC CTRL_CORE_PAD_MCASP1_AXR10 B13 mcasp1_axr10 mcasp6_aclkx mcasp6_aclkr spi3_d0 vin6a_d13 timer7 gpio5_12 Driver off
0x16E0 CTRL_CORE_PAD_MCASP1_AXR11 A12 mcasp1_axr11 mcasp6_fsx mcasp6_fsr spi3_cs0 vin6a_d12 timer8 gpio4_17 Driver off
0x16E4 CTRL_CORE_PAD_MCASP1_AXR12 E14 mcasp1_axr12 mcasp7_axr0 spi3_cs1 vin6a_d11 timer9 gpio4_18 Driver off
0x16E8 CTRL_CORE_PAD_MCASP1_AXR13 A13 mcasp1_axr13 mcasp7_axr1 vin6a_d10 timer10 gpio6_4 Driver off
0x16EC CTRL_CORE_PAD_MCASP1_AXR14 G14 mcasp1_axr14 mcasp7_aclkx mcasp7_aclkr vin6a_d9 timer11 gpio6_5 Driver off
0x16F0 CTRL_CORE_PAD_MCASP1_AXR15 F14 mcasp1_axr15 mcasp7_fsx mcasp7_fsr vin6a_d8 timer12 gpio6_6 Driver off
0x16F4 CTRL_CORE_PAD_MCASP2_ACLKX A19 mcasp2_aclkx vin6a_d7 Driver off
0x16F8 CTRL_CORE_PAD_MCASP2_FSX A18 mcasp2_fsx vin6a_d6 Driver off
0x16FC CTRL_CORE_PAD_MCASP2_ACLKR E15 mcasp2_aclkr mcasp8_axr2 vout2_d8 vin4a_d8 Driver off
0x1700 CTRL_CORE_PAD_MCASP2_FSR A20 mcasp2_fsr mcasp8_axr3 vout2_d9 vin4a_d9 Driver off
0x1704 CTRL_CORE_PAD_MCASP2_AXR0 B15 mcasp2_axr0 vout2_d10 vin4a_d10 Driver off
0x1708 CTRL_CORE_PAD_MCASP2_AXR1 A15 mcasp2_axr1 vout2_d11 vin4a_d11 Driver off
0x170C CTRL_CORE_PAD_MCASP2_AXR2 C15 mcasp2_axr2 mcasp3_axr2 vin6a_d5 gpio6_8 Driver off
0x1710 CTRL_CORE_PAD_MCASP2_AXR3 A16 mcasp2_axr3 mcasp3_axr3 vin6a_d4 gpio6_9 Driver off
0x1714 CTRL_CORE_PAD_MCASP2_AXR4 D15 mcasp2_axr4 mcasp8_axr0 vout2_d12 vin4a_d12 gpio1_4 Driver off
0x1718 CTRL_CORE_PAD_MCASP2_AXR5 B16 mcasp2_axr5 mcasp8_axr1 vout2_d13 vin4a_d13 gpio6_7 Driver off
0x171C CTRL_CORE_PAD_MCASP2_AXR6 B17 mcasp2_axr6 mcasp8_aclkx mcasp8_aclkr vout2_d14 vin4a_d14 gpio2_29 Driver off
0x1720 CTRL_CORE_PAD_MCASP2_AXR7 A17 mcasp2_axr7 mcasp8_fsx mcasp8_fsr vout2_d15 vin4a_d15 gpio1_5 Driver off
0x1724 CTRL_CORE_PAD_MCASP3_ACLKX B18 mcasp3_aclkx mcasp3_aclkr mcasp2_axr12 uart7_rxd vin6a_d3 gpio5_13 Driver off
0x1728 CTRL_CORE_PAD_MCASP3_FSX F15 mcasp3_fsx mcasp3_fsr mcasp2_axr13 uart7_txd vin6a_d2 gpio5_14 Driver off
0x172C CTRL_CORE_PAD_MCASP3_AXR0 B19 mcasp3_axr0 mcasp2_axr14 uart7_ctsn uart5_rxd vin6a_d1 Driver off
0x1730 CTRL_CORE_PAD_MCASP3_AXR1 C17 mcasp3_axr1 mcasp2_axr15 uart7_rtsn uart5_txd vin6a_d0 vin5a_fld0 Driver off
0x1734 CTRL_CORE_PAD_MCASP4_ACLKX C18 mcasp4_aclkx mcasp4_aclkr spi3_sclk uart8_rxd i2c4_sda vout2_d16 vin4a_d16 vin5a_d15 Driver off
0x1738 CTRL_CORE_PAD_MCASP4_FSX A21 mcasp4_fsx mcasp4_fsr spi3_d1 uart8_txd i2c4_scl vout2_d17 vin4a_d17 vin5a_d14 Driver off
0x173C CTRL_CORE_PAD_MCASP4_AXR0 G16 mcasp4_axr0 spi3_d0 uart8_ctsn uart4_rxd vout2_d18 vin4a_d18 vin5a_d13 Driver off
0x1740 CTRL_CORE_PAD_MCASP4_AXR1 D17 mcasp4_axr1 spi3_cs0 uart8_rtsn uart4_txd vout2_d19 vin4a_d19 vin5a_d12 Driver off
0x1744 CTRL_CORE_PAD_MCASP5_ACLKX AA3 mcasp5_aclkx mcasp5_aclkr spi4_sclk uart9_rxd i2c5_sda vout2_d20 vin4a_d20 vin5a_d11 Driver off
0x1748 CTRL_CORE_PAD_MCASP5_FSX AB9 mcasp5_fsx mcasp5_fsr spi4_d1 uart9_txd i2c5_scl vout2_d21 vin4a_d21 vin5a_d10 Driver off
0x174C CTRL_CORE_PAD_MCASP5_AXR0 AB3 mcasp5_axr0 spi4_d0 uart9_ctsn uart3_rxd vout2_d22 vin4a_d22 vin5a_d9 Driver off
0x1750 CTRL_CORE_PAD_MCASP5_AXR1 AA4 mcasp5_axr1 spi4_cs0 uart9_rtsn uart3_txd vout2_d23 vin4a_d23 vin5a_d8 Driver off
0x1754 CTRL_CORE_PAD_MMC1_CLK W6 mmc1_clk gpio6_21 Driver off
0x1758 CTRL_CORE_PAD_MMC1_CMD Y6 mmc1_cmd gpio6_22 Driver off
0x175C CTRL_CORE_PAD_MMC1_DAT0 AA6 mmc1_dat0 gpio6_23 Driver off
0x1760 CTRL_CORE_PAD_MMC1_DAT1 Y4 mmc1_dat1 gpio6_24 Driver off
0x1764 CTRL_CORE_PAD_MMC1_DAT2 AA5 mmc1_dat2 gpio6_25 Driver off
0x1768 CTRL_CORE_PAD_MMC1_DAT3 Y3 mmc1_dat3 gpio6_26 Driver off
0x176C CTRL_CORE_PAD_MMC1_SDCD W7 mmc1_sdcd uart6_rxd i2c4_sda gpio6_27 Driver off
0x1770 CTRL_CORE_PAD_MMC1_SDWP Y9 mmc1_sdwp uart6_txd i2c4_scl gpio6_28 Driver off
0x1774 CTRL_CORE_PAD_GPIO6_10 AC5 gpio6_10 mdio_mclk i2c3_sda usb3_ulpi_d7 vin2b_hsync1 vin5a_clk0 ehrpwm2A gpio6_10 Driver off
0x1778 CTRL_CORE_PAD_GPIO6_11 AB4 gpio6_11 mdio_d i2c3_scl usb3_ulpi_d6 vin2b_vsync1 vin5a_de0 ehrpwm2B gpio6_11 Driver off
0x177C CTRL_CORE_PAD_MMC3_CLK AD4 mmc3_clk usb3_ulpi_d5 vin2b_d7 vin5a_d7 ehrpwm2_tripzone_input gpio6_29 Driver off
0x1780 CTRL_CORE_PAD_MMC3_CMD AC4 mmc3_cmd spi3_sclk usb3_ulpi_d4 vin2b_d6 vin5a_d6 eCAP2_in_PWM2_out gpio6_30 Driver off
0x1784 CTRL_CORE_PAD_MMC3_DAT0 AC7 mmc3_dat0 spi3_d1 uart5_rxd usb3_ulpi_d3 vin2b_d5 vin5a_d5 eQEP3A_in gpio6_31 Driver off
0x1788 CTRL_CORE_PAD_MMC3_DAT1 AC6 mmc3_dat1 spi3_d0 uart5_txd usb3_ulpi_d2 vin2b_d4 vin5a_d4 eQEP3B_in gpio7_0 Driver off
0x178C CTRL_CORE_PAD_MMC3_DAT2 AC9 mmc3_dat2 spi3_cs0 uart5_ctsn usb3_ulpi_d1 vin2b_d3 vin5a_d3 eQEP3_index gpio7_1 Driver off
0x1790 CTRL_CORE_PAD_MMC3_DAT3 AC3 mmc3_dat3 spi3_cs1 uart5_rtsn usb3_ulpi_d0 vin2b_d2 vin5a_d2 eQEP3_strobe gpio7_2 Driver off
0x1794 CTRL_CORE_PAD_MMC3_DAT4 AC8 mmc3_dat4 spi4_sclk uart10_rxd usb3_ulpi_nxt vin2b_d1 vin5a_d1 ehrpwm3A gpio1_22 Driver off
0x1798 CTRL_CORE_PAD_MMC3_DAT5 AD6 mmc3_dat5 spi4_d1 uart10_txd usb3_ulpi_dir vin2b_d0 vin5a_d0 ehrpwm3B gpio1_23 Driver off
0x179C CTRL_CORE_PAD_MMC3_DAT6 AB8 mmc3_dat6 spi4_d0 uart10_ctsn usb3_ulpi_stp vin2b_de1 vin5a_hsync0 ehrpwm3_tripzone_input gpio1_24 Driver off
0x17A0 CTRL_CORE_PAD_MMC3_DAT7 AB5 mmc3_dat7 spi4_cs0 uart10_rtsn usb3_ulpi_clk vin2b_clk1 vin5a_vsync0 eCAP3_in_PWM3_out gpio1_25 Driver off
0x17A4 CTRL_CORE_PAD_SPI1_SCLK A25 spi1_sclk gpio7_7 Driver off
0x17A8 CTRL_CORE_PAD_SPI1_D1 F16 spi1_d1 gpio7_8 Driver off
0x17AC CTRL_CORE_PAD_SPI1_D0 B25 spi1_d0 gpio7_9 Driver off
0x17B0 CTRL_CORE_PAD_SPI1_CS0 A24 spi1_cs0 gpio7_10 Driver off
0x17B4 CTRL_CORE_PAD_SPI1_CS1 A22 spi1_cs1 sata1_led spi2_cs1 gpio7_11 Driver off
0x17B8 CTRL_CORE_PAD_SPI1_CS2 B21 spi1_cs2 uart4_rxd mmc3_sdcd spi2_cs2 dcan2_tx mdio_mclk hdmi1_hpd gpio7_12 Driver off
0x17BC CTRL_CORE_PAD_SPI1_CS3 B20 spi1_cs3 uart4_txd mmc3_sdwp spi2_cs3 dcan2_rx mdio_d hdmi1_cec gpio7_13 Driver off
0x17C0 CTRL_CORE_PAD_SPI2_SCLK A26 spi2_sclk uart3_rxd gpio7_14 Driver off
0x17C4 CTRL_CORE_PAD_SPI2_D1 B22 spi2_d1 uart3_txd gpio7_15 Driver off
0x17C8 CTRL_CORE_PAD_SPI2_D0 G17 spi2_d0 uart3_ctsn uart5_rxd gpio7_16 Driver off
0x17CC CTRL_CORE_PAD_SPI2_CS0 B24 spi2_cs0 uart3_rtsn uart5_txd gpio7_17 Driver off
0x17D0 CTRL_CORE_PAD_DCAN1_TX G20 dcan1_tx uart8_rxd mmc2_sdcd hdmi1_hpd gpio1_14 Driver off
0x17D4 CTRL_CORE_PAD_DCAN1_RX G19 dcan1_rx uart8_txd mmc2_sdwp sata1_led hdmi1_cec gpio1_15 Driver off
0x17E0 CTRL_CORE_PAD_UART1_RXD B27 uart1_rxd mmc4_sdcd gpio7_22 Driver off
0x17E4 CTRL_CORE_PAD_UART1_TXD C26 uart1_txd mmc4_sdwp gpio7_23 Driver off
0x17E8 CTRL_CORE_PAD_UART1_CTSN E25 uart1_ctsn uart9_rxd mmc4_clk gpio7_24 Driver off
0x17EC CTRL_CORE_PAD_UART1_RTSN C27 uart1_rtsn uart9_txd mmc4_cmd gpio7_25 Driver off
0x17F0 CTRL_CORE_PAD_UART2_RXD D28 uart3_ctsn uart3_rctx mmc4_dat0 uart2_rxd uart1_dcdn gpio7_26 Driver off
0x17F4 CTRL_CORE_PAD_UART2_TXD D26 uart2_txd uart3_rtsn uart3_sd mmc4_dat1 uart2_txd uart1_dsrn gpio7_27 Driver off
0x17F8 CTRL_CORE_PAD_UART2_CTSN D27 uart2_ctsn uart3_rxd mmc4_dat2 uart10_rxd uart1_dtrn gpio1_16 Driver off
0x17FC CTRL_CORE_PAD_UART2_RTSN C28 uart2_rtsn uart3_txd uart3_irtx mmc4_dat3 uart10_txd uart1_rin gpio1_17 Driver off
0x1800 CTRL_CORE_PAD_I2C1_SDA C21 i2c1_sda
0x1804 CTRL_CORE_PAD_I2C1_SCL C20 i2c1_scl
0x1808 CTRL_CORE_PAD_I2C2_SDA C25 i2c2_sda hdmi1_ddc_scl Driver off
0x180C CTRL_CORE_PAD_I2C2_SCL F17 i2c2_scl hdmi1_ddc_sda Driver off
0x1818 CTRL_CORE_PAD_WAKEUP0 AD17 Wakeup0 dcan1_rx gpio1_0 Driver off
0x181C CTRL_CORE_PAD_WAKEUP1 AC17 Wakeup1 dcan2_rx gpio1_1 Driver off
0x1820 CTRL_CORE_PAD_WAKEUP2 AB16 Wakeup2 sys_nirq2 gpio1_2 Driver off
0x1824 CTRL_CORE_PAD_WAKEUP3 AC16 Wakeup3 sys_nirq1 gpio1_3 Driver off
0x1828 CTRL_CORE_PAD_ON_OFF Y11 on_off
0x182C CTRL_CORE_PAD_RTC_PORZ AB17 rtc_porz
0x1830 CTRL_CORE_PAD_TMS F18 tms
0x1834 CTRL_CORE_PAD_TDI D23 tdi gpio8_27
0x1838 CTRL_CORE_PAD_TDO F19 tdo gpio8_28
0x183C CTRL_CORE_PAD_TCLK E20 tclk
0x1840 CTRL_CORE_PAD_TRSTN D20 trstn
0x1844 CTRL_CORE_PAD_RTCK E18 rtck gpio8_29
0x1848 CTRL_CORE_PAD_EMU0 G21 emu0 gpio8_30
0x184C CTRL_CORE_PAD_EMU1 D24 emu1 gpio8_31
0x185C CTRL_CORE_PAD_RESETN E23 resetn
0x1860 CTRL_CORE_PAD_NMIN_DSP D21 nmin_dsp
0x1864 CTRL_CORE_PAD_RSTOUTN F23 rstoutn
  1. NA in table stands for Not Applicable.

4.4 Signal Descriptions

Many signals are available on multiple pins, according to the software configuration of the pin multiplexing options.

  1. SIGNAL NAME: The name of the signal passing through the pin.

      NOTE

      The subsystem multiplexing signals are not described in Table 4-2 and Table 4-3.
  2. DESCRIPTION: Description of the signal
  3. TYPE: Signal direction and type:
    • I = Input
    • O = Output
    • IO = Input or output
    • D = Open Drain
    • DS = Differential Signaling
    • A = Analog
    • PWR = Power
    • GND = Ground
  4. BALL: Associated ball(s) number

NOTE

For more information, see the Control Module / Control Module Register Manual section of the device TRM.

4.4.1 Video Input Port (VIP)

NOTE

For more information, see the Video Input Port (VIP) section of the device TRM.

CAUTION

The I/O timings provided in Section 7Timing Requirements and Switching Characteristics are applicable for all combinations of signals for vin1, vin5 and vin6. However, the timings are valid only for vin2, vin3, and vin4 if signals within a single IOSET are used. The IOSETs are defined in the Table 7-4, Table 7-5 and Table 7-6.

Table 4-4 VIP Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
Video Input 1 (VIP1)
vin1a_clk0 Video Input 1 Port A Clock input.Input clock for 8-bit 16-bit or 24-bit Port A video capture. Input data is sampled on the CLK0 edge. I AG8
vin1a_de0 Video Input 1 Port A Data Enable input I AD9
vin1a_fld0 Video Input 1 Port A Field ID input I AF9
vin1a_hsync0 Video Input 1 Port A Horizontal Sync input I AE9
vin1a_vsync0 Video Input 1 Port A Vertical Sync input I AF8
vin1a_d0 Video Input 1 Port A Data input I AE8
vin1a_d1 Video Input 1 Port A Data input I AD8
vin1a_d2 Video Input 1 Port A Data input I AG7
vin1a_d3 Video Input 1 Port A Data input I AH6
vin1a_d4 Video Input 1 Port A Data input I AH3
vin1a_d5 Video Input 1 Port A Data input I AH5
vin1a_d6 Video Input 1 Port A Data input I AG6
vin1a_d7 Video Input 1 Port A Data input I AH4
vin1a_d8 Video Input 1 Port A Data input I AG4
vin1a_d9 Video Input 1 Port A Data input I AG2
vin1a_d10 Video Input 1 Port A Data input I AG3
vin1a_d11 Video Input 1 Port A Data input I AG5
vin1a_d12 Video Input 1 Port A Data input I AF2
vin1a_d13 Video Input 1 Port A Data input I AF6
vin1a_d14 Video Input 1 Port A Data input I AF3
vin1a_d15 Video Input 1 Port A Data input I AF4
vin1a_d16 Video Input 1 Port A Data input I AF1
vin1a_d17 Video Input 1 Port A Data input I AE3
vin1a_d18 Video Input 1 Port A Data input I AE5
vin1a_d19 Video Input 1 Port A Data input I AE1
vin1a_d20 Video Input 1 Port A Data input I AE2
vin1a_d21 Video Input 1 Port A Data input I AE6
vin1a_d22 Video Input 1 Port A Data input I AD2
vin1a_d23 Video Input 1 Port A Data input I AD3
vin1b_hsync1 Video Input 1 Port B Horizontal Sync input I N6/ AD9
vin1b_vsync1 Video Input 1 Port B Vertical Sync input I AF9
vin1b_fld1 Video Input 1 Port B Field ID input I AE9
vin1b_de1 Video Input 1 Port B Data Enable input I AF8/ M4
vin1b_clk1 Video Input 1 Port B Clock input I AH7
vin1b_d0 Video Input 1 Port B Data input I AF4/ AD3
vin1b_d1 Video Input 1 Port B Data input I AF3/ AD2
vin1b_d2 Video Input 1 Port B Data input I AF6/ AE6
vin1b_d3 Video Input 1 Port B Data input I AF2/ AE2
vin1b_d4 Video Input 1 Port B Data input I AG5/ AE1
vin1b_d5 Video Input 1 Port B Data input I AG3/ AE5
vin1b_d6 Video Input 1 Port B Data input I AG2/ AE3
vin1b_d7 Video Input 1 Port B Data input I AG4/ AF1
Video Input 2 (VIP1)
vin2a_clk0 Video Input 2 Port A Clock input. I E1 / V1
vin2a_de0 Video Input 2 Port A Data Enable input I G2 / V7
vin2a_fld0 Video Input 2 Port A Field ID input I G2 / H7 / W2
vin2a_hsync0 Video Input 2 Port A Horizontal Sync input I G1 / U7
vin2a_vsync0 Video Input 2 Port A Vertical Sync input I G6 / V6
vin2a_d0 Video Input 2 Port A Data input I F2 / U4
vin2a_d1 Video Input 2 Port A Data input I F3 / V2
vin2a_d2 Video Input 2 Port A Data input I D1 / Y1
vin2a_d3 Video Input 2 Port A Data input I E2 / W9
vin2a_d4 Video Input 2 Port A Data input I D2 / V9
vin2a_d5 Video Input 2 Port A Data input I F4 / U5
vin2a_d6 Video Input 2 Port A Data input I C1 / V5
vin2a_d7 Video Input 2 Port A Data input I E4 / V4
vin2a_d8 Video Input 2 Port A Data input I F5 / V3
vin2a_d9 Video Input 2 Port A Data input I E6 / Y2
vin2a_d10 Video Input 2 Port A Data input I D3 / U6
vin2a_d11 Video Input 2 Port A Data input I F6 / U3
vin2a_d12 Video Input 2 Port A Data input I D5
vin2a_d13 Video Input 2 Port A Data input I C2
vin2a_d14 Video Input 2 Port A Data input I C3
vin2a_d15 Video Input 2 Port A Data input I C4
vin2a_d16 Video Input 2 Port A Data input I B2
vin2a_d17 Video Input 2 Port A Data input I D6
vin2a_d18 Video Input 2 Port A Data input I C5
vin2a_d19 Video Input 2 Port A Data input I A3
vin2a_d20 Video Input 2 Port A Data input I B3
vin2a_d21 Video Input 2 Port A Data input I B4
vin2a_d22 Video Input 2 Port A Data input I B5
vin2a_d23 Video Input 2 Port A Data input I A4
vin2b_clk1 Video Input 2 Port B Clock input I AB5/ H7
vin2b_de1 Video Input 2 Port B Data Enable input I AB8/ G2
vin2b_fld1 Video Input 2 Port B Field ID input I G2
vin2b_hsync1 Video Input 2 Port B Horizontal Sync input I AC5/ G1
vin2b_vsync1 Video Input 2 Port B Vertical Sync input I AB4/ G6
vin2b_d0 Video Input 2 Port B Data input I AD6/ A4
vin2b_d1 Video Input 2 Port B Data input I AC8/ B5
vin2b_d2 Video Input 2 Port B Data input I AC3/ B4
vin2b_d3 Video Input 2 Port B Data input I AC9/ B3
vin2b_d4 Video Input 2 Port B Data input I AC6/ A3
vin2b_d5 Video Input 2 Port B Data input I AC7/ C5
vin2b_d6 Video Input 2 Port B Data input I AC4/ D6
vin2b_d7 Video Input 2 Port B Data input I AD4/ B2
Video Input 3 (VIP2)
vin3a_clk0 Video Input 3 Port A Clock input I B11/ AH7/ P1
vin3a_de0 Video Input 3 Port A Data Enable input I N9/ B3/ B10
vin3a_fld0 Video Input 3 Port A Field ID input I P9/ B4/ D11
vin3a_hsync0 Video Input 3 Port A Horizontal Sync input I N7/ B5/ C11
vin3a_vsync0 Video Input 3 Port A Vertical Sync input I R4/ A4/ E11
vin3a_d0 Video Input 3 Port A Data input I M6/ AF1/ B7
vin3a_d1 Video Input 3 Port A Data input I M2/ AE3/ B8
vin3a_d2 Video Input 3 Port A Data input I L5/ AE5/ A7
vin3a_d3 Video Input 3 Port A Data input I M1/ AE1/ A8
vin3a_d4 Video Input 3 Port A Data input I L6/ AE2/ C9
vin3a_d5 Video Input 3 Port A Data input I L4/ AE6/ A9
vin3a_d6 Video Input 3 Port A Data input I L3/ AD2/ B9
vin3a_d7 Video Input 3 Port A Data input I L2/ AD3/ A10
vin3a_d8 Video Input 3 Port A Data input I L1/ B2/ E8
vin3a_d9 Video Input 3 Port A Data input I K2/ D6/ D9
vin3a_d10 Video Input 3 Port A Data input I J1/ C5/ D7
vin3a_d11 Video Input 3 Port A Data input I J2/ A3/ D8
vin3a_d12 Video Input 3 Port A Data input I H1/ B3/ A5
vin3a_d13 Video Input 3 Port A Data input I J3/ B4/ C6
vin3a_d14 Video Input 3 Port A Data input I H2/ B5/ C8
vin3a_d15 Video Input 3 Port A Data input I H3/ A4/ C7
vin3a_d16 Video Input 3 Port A Data input I R6/ F11
vin3a_d17 Video Input 3 Port A Data input I T9/ G10
vin3a_d18 Video Input 3 Port A Data input I T6/ F10
vin3a_d19 Video Input 3 Port A Data input I T7/ G11
vin3a_d20 Video Input 3 Port A Data input I P6/ E9
vin3a_d21 Video Input 3 Port A Data input I R9/ F9
vin3a_d22 Video Input 3 Port A Data input I R5/ F8
vin3a_d23 Video Input 3 Port A Data input I P5/ E7
vin3b_clk1 Video Input 3 Port B Clock input I P7/ M4
vin3b_de1 Video Input 3 Port B Data Enable input I N6
vin3b_fld1 Video Input 3 Port A Field ID input I M4
vin3b_hsync1 Video Input 3 Port A Horizontal Sync input I H5
vin3b_vsync1 Video Input 3 Port A Vertical Sync input I H6
vin3b_d0 Video Input 3 Port B Data input I K7
vin3b_d1 Video Input 3 Port B Data input I M7
vin3b_d2 Video Input 3 Port B Data input I J5
vin3b_d3 Video Input 3 Port B Data input I K6
vin3b_d4 Video Input 3 Port B Data input I J7
vin3b_d5 Video Input 3 Port B Data input I J4
vin3b_d6 Video Input 3 Port B Data input I J6
vin3b_d7 Video Input 3 Port B Data input I H4
Video Input 4 (VIP2)
vin4a_clk0 Video Input 4 Port A Clock input I P4/ B26/ B11
vin4a_de0 Video Input 4 Port A Data Enable input I H6/ C23/ B10/ P7
vin4a_fld0 Video Input 4 Port A Field ID input I J7/ F21/ P9/ D11
vin4a_hsync0 Video Input 4 Port A Horizontal Sync input I R3/ E21/ C11/ P7
vin4a_vsync0 Video Input 4 Port A Vertical Sync input I T2/ F20/ E11/ N1
vin4a_d0 Video Input 4 Port A Data input I R6/ B7/ B14
vin4a_d1 Video Input 4 Port A Data input I T9/ B8/ J14
vin4a_d2 Video Input 4 Port A Data input I T6/ A7/ G13
vin4a_d3 Video Input 4 Port A Data input I T7/ A8/ J11
vin4a_d4 Video Input 4 Port A Data input I P6/ C9/ E12
vin4a_d5 Video Input 4 Port A Data input I R9/ A9/ F13
vin4a_d6 Video Input 4 Port A Data input I R5/ B9/ C12
vin4a_d7 Video Input 4 Port A Data input I P5/ A10/ D12
vin4a_d8 Video Input 4 Port A Data input I E8/ U2/ E15
vin4a_d9 Video Input 4 Port A Data input I D9/ U1/ A20
vin4a_d10 Video Input 4 Port A Data input I D7/ P3/ B15
vin4a_d11 Video Input 4 Port A Data input I D8/ R2/ A15
vin4a_d12 Video Input 4 Port A Data input I A5/ K7/ D15
vin4a_d13 Video Input 4 Port A Data input I C6/ M7/ B16
vin4a_d14 Video Input 4 Port A Data input I C8/ J5/ B17
vin4a_d15 Video Input 4 Port A Data input I C7/ K6/ A17
vin4a_d16 Video Input 4 Port A Data input I C18/ F11
vin4a_d17 Video Input 4 Port A Data input I A21/ G10
vin4a_d18 Video Input 4 Port A Data input I G16/ F10
vin4a_d19 Video Input 4 Port A Data input I D17/ G11
vin4a_d20 Video Input 4 Port A Data input I AA3/ E9
vin4a_d21 Video Input 4 Port A Data input I AB9/ F9
vin4a_d22 Video Input 4 Port A Data input I AB3/ F8
vin4a_d23 Video Input 4 Port A Data input I AA4/ E7
vin4b_clk1 Video Input 4 Port B Clock input I N9/ V1
vin4b_de1 Video Input 4 Port B Data Enable input I P9/ V7
vin4b_fld1 Video Input 4 Port B Field ID input I P4/ W2
vin4b_hsync1 Video Input 4 Port B Horizontal Sync input I N7/ U7
vin4b_vsync1 Video Input 4 Port B Vertical Sync input I R4/ V6
vin4b_d0 Video Input 4 Port B Data input I R6/ U4
vin4b_d1 Video Input 4 Port B Data input I T9/ V2
vin4b_d2 Video Input 4 Port B Data input I T6/ Y1
vin4b_d3 Video Input 4 Port B Data input I T7/ W9
vin4b_d4 Video Input 4 Port B Data input I P6/ V9
vin4b_d5 Video Input 4 Port B Data input I R9/ U5
vin4b_d6 Video Input 4 Port B Data input I R5/ V5
vin4b_d7 Video Input 4 Port B Data input I P5/ V4
Video Input 5 (VIP3)
vin5a_clk0 Video Input 5 Port A Clock input I AC5
vin5a_de0 Video Input 5 Port A Data Enable input I AB4
vin5a_fld0 Video Input 5 Port A Field ID input I C17
vin5a_hsync0 Video Input 5 Port A Horizontal Sync input I AB8
vin5a_vsync0 Video Input 5 Port A Vertical Sync input I AB5
vin5a_d0 Video Input 5 Port A Data input I AD6
vin5a_d1 Video Input 5 Port A Data input I AC8
vin5a_d2 Video Input 5 Port A Data input I AC3
vin5a_d3 Video Input 5 Port A Data input I AC9
vin5a_d4 Video Input 5 Port A Data input I AC6
vin5a_d5 Video Input 5 Port A Data input I AC7
vin5a_d6 Video Input 5 Port A Data input I AC4
vin5a_d7 Video Input 5 Port A Data input I AD4
vin5a_d8 Video Input 5 Port A Data input I AA4
vin5a_d9 Video Input 5 Port A Data input I AB3
vin5a_d10 Video Input 5 Port A Data input I AB9
vin5a_d11 Video Input 5 Port A Data input I AA3
vin5a_d12 Video Input 5 Port A Data input I D17
vin5a_d13 Video Input 5 Port A Data input I G16
vin5a_d14 Video Input 5 Port A Data input I A21
vin5a_d15 Video Input 5 Port A Data input I C18
Video Input 6 (VIP3)
vin6a_clk0 Video Input 6 Port A Clock input I E17
vin6a_de0 Video Input 6 Port A Data Enable input I D14
vin6a_fld0 Video Input 6 Port A Field ID input I C14
vin6a_hsync0 Video Input 6 Port A Horizontal Sync input I F12
vin6a_vsync0 Video Input 6 Port A Vertical Sync input I G12
vin6a_d0 Video Input 6 Port A Data input I C17/ D18
vin6a_d1 Video Input 6 Port A Data input I B19
vin6a_d2 Video Input 6 Port A Data input I F15
vin6a_d3 Video Input 6 Port A Data input I B18
vin6a_d4 Video Input 6 Port A Data input I A16
vin6a_d5 Video Input 6 Port A Data input I C15
vin6a_d6 Video Input 6 Port A Data input I A18
vin6a_d7 Video Input 6 Port A Data input I A19
vin6a_d8 Video Input 6 Port A Data input I F14
vin6a_d9 Video Input 6 Port A Data input I G14
vin6a_d10 Video Input 6 Port A Data input I A13
vin6a_d11 Video Input 6 Port A Data input I E14
vin6a_d12 Video Input 6 Port A Data input I A12
vin6a_d13 Video Input 6 Port A Data input I B13
vin6a_d14 Video Input 6 Port A Data input I A11
vin6a_d15 Video Input 6 Port A Data input I B12

4.4.2 Display Subsystem – Video Output Ports

CAUTION

The I/O timings provided in Section 7Timing Requirements and Switching Characteristics are valid only if signals within a single IOSET are used. The IOSETs are defined in the Table 7-19 and Table 7-20.

Table 4-5 DSS Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
DPI Video Output 1
vout1_clk Video Output 1 Clock output O D11
vout1_de Video Output 1 Data Enable output O B10
vout1_fld Video Output 1 Field ID output.This signal is not used for embedded sync modes. O B11
vout1_hsync Video Output 1 Horizontal Sync output.This signal is not used for embedded sync modes. O C11
vout1_vsync Video Output 1 Vertical Sync output.This signal is not used for embedded sync modes. O E11
vout1_d0 Video Output 1 Data output O F11
vout1_d1 Video Output 1 Data output O G10
vout1_d2 Video Output 1 Data output O F10
vout1_d3 Video Output 1 Data output O G11
vout1_d4 Video Output 1 Data output O E9
vout1_d5 Video Output 1 Data output O F9
vout1_d6 Video Output 1 Data output O F8
vout1_d7 Video Output 1 Data output O E7
vout1_d8 Video Output 1 Data output O E8
vout1_d9 Video Output 1 Data output O D9
vout1_d10 Video Output 1 Data output O D7
vout1_d11 Video Output 1 Data output O D8
vout1_d12 Video Output 1 Data output O A5
vout1_d13 Video Output 1 Data output O C6
vout1_d14 Video Output 1 Data output O C8
vout1_d15 Video Output 1 Data output O C7
vout1_d16 Video Output 1 Data output O B7
vout1_d17 Video Output 1 Data output O B8
vout1_d18 Video Output 1 Data output O A7
vout1_d19 Video Output 1 Data output O A8
vout1_d20 Video Output 1 Data output O C9
vout1_d21 Video Output 1 Data output O A9
vout1_d22 Video Output 1 Data output O B9
vout1_d23 Video Output 1 Data output O A10
DPI Video Output 2
vout2_clk Video Output 2 Clock output O H7/ B26
vout2_de Video Output 2 Data Enable output O G2/ C23
vout2_fld Video Output 2 Field ID output.This signal is not used for embedded sync modes. O E1/ F21
vout2_hsync Video Output 2 Horizontal Sync output.This signal is not used for embedded sync modes. O G1/ E21
vout2_vsync Video Output 2 Vertical Sync output.This signal is not used for embedded sync modes. O G6/ F20
vout2_d0 Video Output 2 Data output O A4/ B14
vout2_d1 Video Output 2 Data output O B5/ J14
vout2_d2 Video Output 2 Data output O B4/ G13
vout2_d3 Video Output 2 Data output O B3/ J11
vout2_d4 Video Output 2 Data output O A3/ E12
vout2_d5 Video Output 2 Data output O C5/ F13
vout2_d6 Video Output 2 Data output O D6/ C12
vout2_d7 Video Output 2 Data output O B2/ D12
vout2_d8 Video Output 2 Data output O C4/ E15
vout2_d9 Video Output 2 Data output O C3/ A20
vout2_d10 Video Output 2 Data output O C2/ B15
vout2_d11 Video Output 2 Data output O D5/ A15
vout2_d12 Video Output 2 Data output O F6/ D15
vout2_d13 Video Output 2 Data output O D3/ B16
vout2_d14 Video Output 2 Data output O E6/ B17
vout2_d15 Video Output 2 Data output O F5/ A17
vout2_d16 Video Output 2 Data output O E4/ C18
vout2_d17 Video Output 2 Data output O C1/ A21
vout2_d18 Video Output 2 Data output O F4/ G16
vout2_d19 Video Output 2 Data output O D2/ D17
vout2_d20 Video Output 2 Data output O E2/ AA3
vout2_d21 Video Output 2 Data output O D1/ AB9
vout2_d22 Video Output 2 Data output O F3/ AB3
vout2_d23 Video Output 2 Data output O F2/ AA4
DPI Video Output 3
vout3_clk Video Output 3 Clock output O P1/ AF9(1)
vout3_de Video Output 3 Data Enable output O N9/ AD9(1)
vout3_fld Video Output 3 Field ID output.This signal is not used for embedded sync modes. O P9/ AG8(1)
vout3_hsync Video Output 3 Horizontal Sync output.This signal is not used for embedded sync modes. O N7/ AE9(1)
vout3_vsync Video Output 3 Vertical Sync output.This signal is not used for embedded sync modes. O R4/ AF8(1)
vout3_d0 Video Output 3 Data output O M6/ AH4(1)/ AD3(1)
vout3_d1 Video Output 3 Data output O M2/ AG6(1)/ AD2(1)
vout3_d2 Video Output 3 Data output O L5/ AH5(1)/ AE6(1)
vout3_d3 Video Output 3 Data output O M1/ AH3(1)/ AE2(1)
vout3_d4 Video Output 3 Data output O L6/ AH6(1)/ AE1(1)
vout3_d5 Video Output 3 Data output O L4/ AG7(1)/ AE5(1)
vout3_d6 Video Output 3 Data output O L3/ AD8(1)/ AE3(1)
vout3_d7 Video Output 3 Data output O L2/ AE8(1)/ AF1(1)
vout3_d8 Video Output 3 Data output O L1/ AF4(1)
vout3_d9 Video Output 3 Data output O K2/ AF3(1)
vout3_d10 Video Output 3 Data output O J1/ AF6(1)
vout3_d11 Video Output 3 Data output O J2/ AF2(1)
vout3_d12 Video Output 3 Data output O H1/ AG5(1)
vout3_d13 Video Output 3 Data output O J3/ AG3(1)
vout3_d14 Video Output 3 Data output O H2/ AG2(1)
vout3_d15 Video Output 3 Data output O H3/ AG4(1)
vout3_d16 Video Output 3 Data output O R6/ AG8(1)/ AH4(1)
vout3_d17 Video Output 3 Data output O T9/ AD9(1)/ AG6(1)
vout3_d18 Video Output 3 Data output O T6/ AH5(1)
vout3_d19 Video Output 3 Data output O T7/ AH3(1)
vout3_d20 Video Output 3 Data output O P6/ AH6(1)
vout3_d21 Video Output 3 Data output O R9/ AG7(1)
vout3_d22 Video Output 3 Data output O R5/ AD8(1)
vout3_d23 Video Output 3 Data output O P5/ AE8(1)
  1. The VOUT3 interface when multiplexed onto balls mapped to the VDDSHV6 supply rail is restricted to operating in 1.8V mode only (VDDSHV6 must be supplied with 1.8V). 3.3V mode is not supported. This must be considered in the pin mux programming and VDDSHVx supply connections.

4.4.3 Display Subsystem – High-Definition Multimedia Interface (HDMI)

NOTE

For more information, see the Display Subsystem section of the device TRM.

Table 4-6 HDMI Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
hdmi1_cec HDMI consumer electronic control IOD B20/G19
hdmi1_hpd HDMI display hot plug detect IO B21/G20
hdmi1_ddc_scl HDMI display data channel clock IOD C25
hdmi1_ddc_sda HDMI display data channel data IOD F17
hdmi1_clockx HDMI clock differential positive or negative ODS AG16
hdmi1_clocky HDMI clock differential positive or negative ODS AH16
hdmi1_data2x HDMI data 2 differential positive or negative ODS AG19
hdmi1_data2y HDMI data 2 differential positive or negative ODS AH19
hdmi1_data1x HDMI data 1 differential positive or negative ODS AG18
hdmi1_data1y HDMI data 1 differential positive or negative ODS AH18
hdmi1_data0x HDMI data 0 differential positive or negative ODS AG17
hdmi1_data0y HDMI data 0 differential positive or negative ODS AH17

4.4.4 External Memory Interface (EMIF)

NOTE

For more information, see the Memory Subsystem / EMIF Controller section of the device TRM.

Table 4-7 EMIF Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
EMIF Channel 1
ddr1_csn0 EMIF1 Chip Select 0 O AH23
ddr1_cke EMIF1 Clock Enable O AG22
ddr1_ck EMIF1 Clock O AG24
ddr1_nck EMIF1 Negative Clock O AH24
ddr1_odt0 EMIF1 On-Die Termination for Chip Select 0 O AE20
ddr1_casn EMIF1 Column Address Strobe O AC18
ddr1_rasn EMIF1 Row Address Strobe O AF20
ddr1_wen EMIF1 Write Enable O AH21
ddr1_rst EMIF1 Reset output (DDR3-SDRAM only) O AG21
ddr1_ba0 EMIF1 Bank Address O AF17
ddr1_ba1 EMIF1 Bank Address O AE18
ddr1_ba2 EMIF1 Bank Address O AB18
ddr1_a0 EMIF1 Address Bus O AD20
ddr1_a1 EMIF1 Address Bus O AC19
ddr1_a2 EMIF1 Address Bus O AC20
ddr1_a3 EMIF1 Address Bus O AB19
ddr1_a4 EMIF1 Address Bus O AF21
ddr1_a5 EMIF1 Address Bus O AH22
ddr1_a6 EMIF1 Address Bus O AG23
ddr1_a7 EMIF1 Address Bus O AE21
ddr1_a8 EMIF1 Address Bus O AF22
ddr1_a9 EMIF1 Address Bus O AE22
ddr1_a10 EMIF1 Address Bus O AD21
ddr1_a11 EMIF1 Address Bus O AD22
ddr1_a12 EMIF1 Address Bus O AC21
ddr1_a13 EMIF1 Address Bus O AF18
ddr1_a14 EMIF1 Address Bus O AE17
ddr1_a15 EMIF1 Address Bus O AD18
ddr1_d0 EMIF1 Data Bus IO AF25
ddr1_d1 EMIF1 Data Bus IO AF26
ddr1_d2 EMIF1 Data Bus IO AG26
ddr1_d3 EMIF1 Data Bus IO AH26
ddr1_d4 EMIF1 Data Bus IO AF24
ddr1_d5 EMIF1 Data Bus IO AE24
ddr1_d6 EMIF1 Data Bus IO AF23
ddr1_d7 EMIF1 Data Bus IO AE23
ddr1_d8 EMIF1 Data Bus IO AC23
ddr1_d9 EMIF1 Data Bus IO AF27
ddr1_d10 EMIF1 Data Bus IO AG27
ddr1_d11 EMIF1 Data Bus IO AF28
ddr1_d12 EMIF1 Data Bus IO AE26
ddr1_d13 EMIF1 Data Bus IO AC25
ddr1_d14 EMIF1 Data Bus IO AC24
ddr1_d15 EMIF1 Data Bus IO AD25
ddr1_d16 EMIF1 Data Bus IO V20
ddr1_d17 EMIF1 Data Bus IO W20
ddr1_d18 EMIF1 Data Bus IO AB28
ddr1_d19 EMIF1 Data Bus IO AC28
ddr1_d20 EMIF1 Data Bus IO AC27
ddr1_d21 EMIF1 Data Bus IO Y19
ddr1_d22 EMIF1 Data Bus IO AB27
ddr1_d23 EMIF1 Data Bus IO Y20
ddr1_d24 EMIF1 Data Bus IO AA23
ddr1_d25 EMIF1 Data Bus IO Y22
ddr1_d26 EMIF1 Data Bus IO Y23
ddr1_d27 EMIF1 Data Bus IO AA24
ddr1_d28 EMIF1 Data Bus IO Y24
ddr1_d29 EMIF1 Data Bus IO AA26
ddr1_d30 EMIF1 Data Bus IO AA25
ddr1_d31 EMIF1 Data Bus IO AA28
ddr1_ecc_d0 EMIF1 ECC Data Bus IO W22
ddr1_ecc_d1 EMIF1 ECC Data Bus IO V23
ddr1_ecc_d2 EMIF1 ECC Data Bus IO W19
ddr1_ecc_d3 EMIF1 ECC Data Bus IO W23
ddr1_ecc_d4 EMIF1 ECC Data Bus IO Y25
ddr1_ecc_d5 EMIF1 ECC Data Bus IO V24
ddr1_ecc_d6 EMIF1 ECC Data Bus IO V25
ddr1_ecc_d7 EMIF1 ECC Data Bus IO Y26
ddr1_dqm0 EMIF1 Data Mask O AD23
ddr1_dqm1 EMIF1 Data Mask O AB23
ddr1_dqm2 EMIF1 Data Mask O AC26
ddr1_dqm3 EMIF1 Data Mask O AA27
ddr1_dqm_ecc EMIF1 ECC Data Mask O V26
ddr1_dqs0 Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO AH25
ddr1_dqsn0 Data strobe 0 invert IO AG25
ddr1_dqs1 Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO AE27
ddr1_dqsn1 Data strobe 1 invert IO AE28
ddr1_dqs2 Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO AD27
ddr1_dqsn2 Data strobe 2 invert IO AD28
ddr1_dqs3 Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO Y28
ddr1_dqsn3 Data strobe 3 invert IO Y27
ddr1_dqs_ecc EMIF1 ECC Data strobe input/output. This signal is output to the EMIF1 memory when writing and input when reading. IO V27
ddr1_dqsn_ecc EMIF1 ECC Complementary Data strobe IO V28
ddr1_vref0 Reference Power Supply EMIF1 A Y18
EMIF Channel 2
ddr2_csn0 EMIF2 Chip Select 0 O P24
ddr2_cke EMIF2 Clock Enable O U24
ddr2_ck EMIF2 Clock O T28
ddr2_nck EMIF2 Negative Clock O T27
ddr2_odt0 EMIF2 On-Die Termination for Chip Select 0 O R23
ddr2_casn EMIF2 Column Address Strobe O U28
ddr2_rasn EMIF2 Row Address Strobe O T23
ddr2_wen EMIF2 Write Enable O U25
ddr2_rst EMIF2 Reset output (DDR3-SDRAM only) O R24
ddr2_ba0 EMIF2 Bank Address O U23
ddr2_ba1 EMIF2 Bank Address O U27
ddr2_ba2 EMIF2 Bank Address O U26
ddr2_a0 EMIF2 Address Bus O R25
ddr2_a1 EMIF2 Address Bus O R26
ddr2_a2 EMIF2 Address Bus O R28
ddr2_a3 EMIF2 Address Bus O R27
ddr2_a4 EMIF2 Address Bus O P23
ddr2_a5 EMIF2 Address Bus O P22
ddr2_a6 EMIF2 Address Bus O P25
ddr2_a7 EMIF2 Address Bus O N20
ddr2_a8 EMIF2 Address Bus O P27
ddr2_a9 EMIF2 Address Bus O N27
ddr2_a10 EMIF2 Address Bus O N23
ddr2_a11 EMIF2 Address Bus O P26
ddr2_a12 EMIF2 Address Bus O N28
ddr2_a13 EMIF2 Address Bus O T22
ddr2_a14 EMIF2 Address Bus O R22
ddr2_a15 EMIF2 Address Bus O U22
ddr2_d0 EMIF2 Data Bus IO E26
ddr2_d1 EMIF2 Data Bus IO G25
ddr2_d2 EMIF2 Data Bus IO F25
ddr2_d3 EMIF2 Data Bus IO F24
ddr2_d4 EMIF2 Data Bus IO F26
ddr2_d5 EMIF2 Data Bus IO F27
ddr2_d6 EMIF2 Data Bus IO E27
ddr2_d7 EMIF2 Data Bus IO E28
ddr2_d8 EMIF2 Data Bus IO H23
ddr2_d9 EMIF2 Data Bus IO H25
ddr2_d10 EMIF2 Data Bus IO H24
ddr2_d11 EMIF2 Data Bus IO H26
ddr2_d12 EMIF2 Data Bus IO G26
ddr2_d13 EMIF2 Data Bus IO J25
ddr2_d14 EMIF2 Data Bus IO J26
ddr2_d15 EMIF2 Data Bus IO J24
ddr2_d16 EMIF2 Data Bus IO L22
ddr2_d17 EMIF2 Data Bus IO K20
ddr2_d18 EMIF2 Data Bus IO K21
ddr2_d19 EMIF2 Data Bus IO L23
ddr2_d20 EMIF2 Data Bus IO L24
ddr2_d21 EMIF2 Data Bus IO J23
ddr2_d22 EMIF2 Data Bus IO K22
ddr2_d23 EMIF2 Data Bus IO J20
ddr2_d24 EMIF2 Data Bus IO L27
ddr2_d25 EMIF2 Data Bus IO L26
ddr2_d26 EMIF2 Data Bus IO L25
ddr2_d27 EMIF2 Data Bus IO L28
ddr2_d28 EMIF2 Data Bus IO M23
ddr2_d29 EMIF2 Data Bus IO M24
ddr2_d30 EMIF2 Data Bus IO M25
ddr2_d31 EMIF2 Data Bus IO M26
ddr2_dqm0 EMIF2 Data Mask O F28
ddr2_dqm1 EMIF2 Data Mask O G24
ddr2_dqm2 EMIF2 Data Mask O K23
ddr2_dqm3 EMIF2 Data Mask O M22
ddr2_dqs0 Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the EMIF2 memory when writing and input when reading. IO G28
ddr2_dqsn0 Data strobe 0 invert IO G27
ddr2_dqs1 Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the EMIF2 memory when writing and input when reading. IO H27
ddr2_dqsn1 Data strobe 1 invert IO H28
ddr2_dqs2 Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the EMIF2 memory when writing and input when reading. IO K27
ddr2_dqsn2 Data strobe 2 invert IO K28
ddr2_dqs3 Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the EMIF2 memory when writing and input when reading. IO M28
ddr2_dqsn3 Data strobe 3 invert IO M27
ddr2_vref0 Reference Power Supply EMIF2 A N22

NOTE

DDR SDRAM Channel 2 is not supported by Vision High Surround, Vision High and Vision Mid devices.

For more details on the device differentiation, refer to Table 3-1, Device Comparison.

NOTE

The index numbers 1 and 2 which is part of the EMIF1 and EMIF2 signal prefixes (ddr1_* and ddr2_*) listed in Table 4-7, DDR2/DDR3/DDR3L SDRAM Signal Descriptions, column "SIGNAL NAME" not to be confused with DDR1 and DDR2 types of SDRAM memories.

4.4.5 General-Purpose Memory Controller (GPMC)

NOTE

For more information, see the Memory Subsystem / General-Purpose Memory Controller section of the device TRM.

Table 4-8 GPMC Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
gpmc_ad0 GPMC Data 0 in A/D nonmultiplexed mode and additionally Address 1 in A/D multiplexed mode IO M6
gpmc_ad1 GPMC Data 1 in A/D nonmultiplexed mode and additionally Address 2 in A/D multiplexed mode IO M2
gpmc_ad2 GPMC Data 2 in A/D nonmultiplexed mode and additionally Address 3 in A/D multiplexed mode IO L5
gpmc_ad3 GPMC Data 3 in A/D nonmultiplexed mode and additionally Address 4 in A/D multiplexed mode IO M1
gpmc_ad4 GPMC Data 4 in A/D nonmultiplexed mode and additionally Address 5 in A/D multiplexed mode IO L6
gpmc_ad5 GPMC Data 5 in A/D nonmultiplexed mode and additionally Address 6 in A/D multiplexed mode IO L4
gpmc_ad6 GPMC Data 6 in A/D nonmultiplexed mode and additionally Address 7 in A/D multiplexed mode IO L3
gpmc_ad7 GPMC Data 7 in A/D nonmultiplexed mode and additionally Address 8 in A/D multiplexed mode IO L2
gpmc_ad8 GPMC Data 8 in A/D nonmultiplexed mode and additionally Address 9 in A/D multiplexed mode IO L1
gpmc_ad9 GPMC Data 9 in A/D nonmultiplexed mode and additionally Address 10 in A/D multiplexed mode IO K2
gpmc_ad10 GPMC Data 10 in A/D nonmultiplexed mode and additionally Address 11 in A/D multiplexed mode IO J1
gpmc_ad11 GPMC Data 11 in A/D nonmultiplexed mode and additionally Address 12 in A/D multiplexed mode IO J2
gpmc_ad12 GPMC Data 12 in A/D nonmultiplexed mode and additionally Address 13 in A/D multiplexed mode IO H1
gpmc_ad13 GPMC Data 13 in A/D nonmultiplexed mode and additionally Address 14 in A/D multiplexed mode IO J3
gpmc_ad14 GPMC Data 14 in A/D nonmultiplexed mode and additionally Address 15 in A/D multiplexed mode IO H2
gpmc_ad15 GPMC Data 15 in A/D nonmultiplexed mode and additionally Address 16 in A/D multiplexed mode IO H3
gpmc_a0 GPMC Address 0. Only used to effectively address 8-bit data nonmultiplexed memories O R6/ P4
gpmc_a1 GPMC address 1 in A/D nonmultiplexed mode and Address 17 in A/D multiplexed mode O T9/ P1
gpmc_a2 GPMC address 2 in A/D nonmultiplexed mode and Address 18 in A/D multiplexed mode O T6/ N1
gpmc_a3 GPMC address 3 in A/D nonmultiplexed mode and Address 19 in A/D multiplexed mode O T7/ M4
gpmc_a4 GPMC address 4 in A/D nonmultiplexed mode and Address 20 in A/D multiplexed mode O P6
gpmc_a5 GPMC address 5 in A/D nonmultiplexed mode and Address 21 in A/D multiplexed mode O R9
gpmc_a6 GPMC address 6 in A/D nonmultiplexed mode and Address 22 in A/D multiplexed mode O R5
gpmc_a7 GPMC address 7 in A/D nonmultiplexed mode and Address 23 in A/D multiplexed mode O P5
gpmc_a8 GPMC address 8 in A/D nonmultiplexed mode and Address 24 in A/D multiplexed mode O N7
gpmc_a9 GPMC address 9 in A/D nonmultiplexed mode and Address 25 in A/D multiplexed mode O R4
gpmc_a10 GPMC address 10 in A/D nonmultiplexed mode and Address 26 in A/D multiplexed mode O N9
gpmc_a11 GPMC address 11 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O P9
gpmc_a12 GPMC address 12 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O P4
gpmc_a13 GPMC address 13 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O R3/ K7
gpmc_a14 GPMC address 14 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O T2/ M7
gpmc_a15 GPMC address 15 in A/D non-multiplexed mode and unused in A/D multiplexed mode O U2/ J5
gpmc_a16 GPMC address 16 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O U1/ K6
gpmc_a17 GPMC address 17 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O P3/ J7
gpmc_a18 GPMC address 18 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O R2/ J4
gpmc_a19 GPMC address 19 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O K7(3) / J6
gpmc_a20 GPMC address 20 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O M7(3) / H4
gpmc_a21 GPMC address 21 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O J5(3) / H5
gpmc_a22 GPMC address 22 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O K6(3) / H6
gpmc_a23 GPMC address 23 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O J7/ AG5/ N1
gpmc_a24 GPMC address 24 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O J4(3) / AF2
gpmc_a25 GPMC address 25 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O J6(3) / AF6
gpmc_a26 GPMC address 26 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O H4(3) / AF3
gpmc_a27 GPMC address 27 in A/D nonmultiplexed mode and Address 27 in A/D multiplexed mode O H5(3) / AF4
gpmc_cs0 GPMC Chip Select 0 (active low) O T1
gpmc_cs1 GPMC Chip Select 1 (active low) O H6
gpmc_cs2 GPMC Chip Select 2 (active low) O P2
gpmc_cs3 GPMC Chip Select 3 (active low) O P1
gpmc_cs4 GPMC Chip Select 4 (active low) O N6
gpmc_cs5 GPMC Chip Select 5 (active low) O M4
gpmc_cs6 GPMC Chip Select 6 (active low) O N1
gpmc_cs7 GPMC Chip Select 7 (active low) O P7
gpmc_clk(1)(2) GPMC Clock output IO P7
gpmc_advn_ale GPMC address valid active low or address latch enable O N1
gpmc_oen_ren GPMC output enable active low or read enable O M5
gpmc_wen GPMC write enable active low O M3
gpmc_ben0 GPMC lower-byte enable active low O N6
gpmc_ben1 GPMC upper-byte enable active low O M4
gpmc_wait0 GPMC external indication of wait 0 I N2
gpmc_wait1 GPMC external indication of wait 1 I P7/ N1
  1. This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS.
  2. The gpio6_16.clkout1 signal can be used as an “always-on” alternative to gpmc_clk provided that the external device can support the associated timing. See Table 7-26GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Default and Table 7-28GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Alternate for timing information.
  3. The internal pull resistors for balls K7, M7, J5, K6, J4, J6, H4, H5 are permanently disabled when sysboot15 is set to 1 as described in the section Sysboot Configuration of the Device TRM. If internal pull-up/down resistors are desired on these balls then sysboot15 should be set to 0. If gpmc boot mode is used with SYSBOOT15=1 (not recommended) then external pull-downs should be implemented to keep the address bus at logic-0 value during boot since the gpmc ms-address bits are high-z during boot.

 
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