ZHCSIK3A July   2018  – January 2025 TPS650861

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Total Current Consumption
    6. 5.6  Electrical Characteristics: Reference and Monitoring System
    7. 5.7  Electrical Characteristics: Buck Controllers
    8. 5.8  Electrical Characteristics: Synchronous Buck Converters
    9. 5.9  Electrical Characteristics: LDOs
    10. 5.10 Electrical Characteristics: Load Switches
    11. 5.11 Digital Signals: I2C Interface
    12. 5.12 Digital Input Signals (CTLx)
    13. 5.13 Digital Output Signals (IRQB, GPOx)
    14. 5.14 Timing Requirements
    15. 5.15 Switching Characteristics
    16. 5.16 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Programming the TPS650861
    4. 6.4  SMPS Voltage Regulators
      1. 6.4.1 Controller Overview
      2. 6.4.2 Converter Overview
      3. 6.4.3 DVS
      4. 6.4.4 Decay
      5. 6.4.5 Current Limit
    5. 6.5  LDOs and Load Switches
      1. 6.5.1 VTT LDO
      2. 6.5.2 LDOA1–LDOA3
      3. 6.5.3 Load Switches
    6. 6.6  Power Goods (PGOOD or PG) and GPOs
    7. 6.7  One-Time Programmable Memory
    8. 6.8  Power Sequencing and VR Control
      1. 6.8.1 CTLx Sequencing
      2. 6.8.2 PG Sequencing
      3. 6.8.3 Enable Delay
      4. 6.8.4 Power-Up Sequence
      5. 6.8.5 Power-Down Sequence
      6. 6.8.6 Sleep State Entry and Exit
      7. 6.8.7 Emergency Shutdown
    9. 6.9  Device Functional Modes
      1. 6.9.1 Off Mode
      2. 6.9.2 Standby Mode
      3. 6.9.3 Active Mode
    10. 6.10 I2C Interface
      1. 6.10.1 F/S-Mode Protocol
    11. 6.11 I2C Address: 0x5E Register Maps
      1. 6.11.1  Register Map Summary
      2. 6.11.2  DEVICEID1: 1st PMIC Device and Revision ID Register (offset = 00h) [reset = X]
      3. 6.11.3  DEVICEID2: 2nd PMIC Device and Revision ID Register (offset = 01h) [reset = X]
      4. 6.11.4  IRQ: PMIC Interrupt Register (offset = 02h) [reset = 0000 0000]
      5. 6.11.5  IRQ_MASK: PMIC Interrupt Mask Register (offset = 03h) [reset = 1111 1111]
      6. 6.11.6  PMICSTAT: PMIC Status Register (offset = 04h) [reset = 0000 0000]
      7. 6.11.7  SHUTDNSRC: PMIC Shut-Down Event Register (offset = 05h) [reset = 0000 0000]
      8. 6.11.8  BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = X]
      9. 6.11.9  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = X]
      10. 6.11.10 BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = X]
      11. 6.11.11 BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = X]
      12. 6.11.12 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = X]
      13. 6.11.13 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = X]
      14. 6.11.14 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = X]
      15. 6.11.15 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = X]
      16. 6.11.16 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = X]
      17. 6.11.17 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = X]
      18. 6.11.18 DISCHCTRL1: 1st Discharge Control Register (offset = 40h) [reset = X]
      19. 6.11.19 DISCHCTRL2: 2nd Discharge Control Register (offset = 41h) [reset = X]
      20. 6.11.20 DISCHCTRL3: 3rd Discharge Control Register (offset = 42h) [reset = X]
      21. 6.11.21 PG_DELAY1: 1st Power Good Delay Register (offset = 43h) [reset = X]
      22. 6.11.22 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0000 0000]
      23. 6.11.23 BUCK1SLPCTRL: BUCK1 Sleep Control Register (offset = 92h) [reset = X]
      24. 6.11.24 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = X]
      25. 6.11.25 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = X]
      26. 6.11.26 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = X]
      27. 6.11.27 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = X]
      28. 6.11.28 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = X]
      29. 6.11.29 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = X]
      30. 6.11.30 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = X]
      31. 6.11.31 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = X]
      32. 6.11.32 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = X]
      33. 6.11.33 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = X]
      34. 6.11.34 PG_DELAY2: 2nd Power Good Delay Register (offset = 9Dh) [reset = X]
      35. 6.11.35 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = X]
      36. 6.11.36 I2C_RAIL_EN1: 1st VR Pin Enable Override Register (offset = A0h) [reset = X]
      37. 6.11.37 I2C_RAIL_EN2/GPOCTRL: 2nd VR Pin Enable Override and GPO Control Register (offset = A1h) [reset = X]
      38. 6.11.38 PWR_FAULT_MASK1: 1st VR Power Fault Mask Register (offset = A2h) [reset = X]
      39. 6.11.39 PWR_FAULT_MASK2: 2nd VR Power Fault Mask Register (offset = A3h) [reset = X]
      40. 6.11.40 GPO1PG_CTRL1: 1st GPO1 PG Control Register (offset = A4h) [reset = X]
      41. 6.11.41 GPO1PG_CTRL2: 2nd GPO1 PG Control Register (offset = A5h) [reset = X]
      42. 6.11.42 GPO4PG_CTRL1: 1st GPO4 PG Control Register (offset = A6h) [reset = X]
      43. 6.11.43 GPO4PG_CTRL2: 2nd GPO4 PG Control Register (offset = A7h) [reset = X]
      44. 6.11.44 GPO2PG_CTRL1: 1st GPO2 PG Control Register (offset = A8h) [reset = X]
      45. 6.11.45 GPO2PG_CTRL2: 2nd GPO2 PG Control Register (offset = A9h) [reset = X]
      46. 6.11.46 GPO3PG_CTRL1: 1st GPO3 PG Control Register (offset = AAh) [reset = X]
      47. 6.11.47 GPO3PG_CTRL2: 2nd GPO3 PG Control Register (offset = ABh) [reset = X]
      48. 6.11.48 MISCSYSPG Register (offset = ACh) [reset = X]
        1. 6.11.48.1 VTT_DISCH_CTRL Register (offset = ADh) [reset = X]
      49. 6.11.49 LDOA1_SWB2_CTRL: LDOA1 and SWB2 Control Register (offset = AEh) [reset = X]
      50. 6.11.50 PG_STATUS1: 1st Power Good Status Register (offset = B0h) [reset = 0000 0000]
      51. 6.11.51 PG_STATUS2: 2nd Power Good Status Register (offset = B1h) [reset = 0000 0000]
      52. 6.11.52 PWR_FAULT_STATUS1: 1st Power Fault Status Register (offset = B2h) [reset = 0000 0000]
      53. 6.11.53 PWR_FAULT_STATUS2: 2nd Power Fault Status Register (offset = B3h) [reset = 0000 0000]
      54. 6.11.54 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0000 0000]
      55. 6.11.55 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]
      56. 6.11.56 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0000 0000]
    12. 6.12 I2C Address: 0x38 Register Maps
      1. 6.12.1  Register Map Summary
      2. 6.12.2  OTP_CTRL1 (offset = 02h) [reset = 0010 0000]
      3. 6.12.3  OTP_CTRL2 (offset = 03h) [reset = X]
      4. 6.12.4  BUCK1_CTRL_EN1 (offset = 07h) [reset = X]
      5. 6.12.5  BUCK1_CTRL_EN2 (offset = 08h) [reset = X]
      6. 6.12.6  BUCK1_CTRL_EN3 (offset = 09h) [reset = X]
      7. 6.12.7  BUCK2_CTRL_EN1 (offset = 0Ah) [reset = X]
      8. 6.12.8  BUCK2_CTRL_EN2 (offset = 0Bh) [reset = X]
      9. 6.12.9  BUCK2_CTRL_EN3 (offset = 0Ch) [reset = X]
      10. 6.12.10 BUCK3_CTRL_EN1 (offset = 0Ah) [reset = X]
      11. 6.12.11 BUCK3_CTRL_EN2 (offset = 0Eh) [reset = X]
      12. 6.12.12 BUCK3_CTRL_EN3 (offset = 0Fh) [reset = X]
      13. 6.12.13 BUCK4_CTRL_EN1 (offset = 10h) [reset = X]
      14. 6.12.14 BUCK4_CTRL_EN2 (offset = 11h) [reset = X]
      15. 6.12.15 BUCK4_CTRL_EN3 (offset = 12h) [reset = X]
      16. 6.12.16 BUCK5_CTRL_EN1 (offset = 13h) [reset = X]
      17. 6.12.17 BUCK5_CTRL_EN2 (offset = 14h) [reset = X]
      18. 6.12.18 BUCK5_CTRL_EN3 (offset = 15h) [reset = X]
      19. 6.12.19 BUCK6_CTRL_EN1 (offset = 16h) [reset = X]
      20. 6.12.20 BUCK6_CTRL_EN2 (offset = 17h) [reset = X]
      21. 6.12.21 BUCK6_CTRL_EN3 (offset = 18h) [reset = X]
      22. 6.12.22 SWA1_CTRL_EN1 (offset = 19h) [reset = X]
      23. 6.12.23 SWA1_CTRL_EN2 (offset = 1Ah) [reset = X]
      24. 6.12.24 SWA1_CTRL_EN3 (offset = 1Bh) [reset = X]
      25. 6.12.25 LDOA2_CTRL_EN1 (offset = 1Ch) [reset = X]
      26. 6.12.26 LDOA2_CTRL_EN2 (offset = 1Dh) [reset = X]
      27. 6.12.27 LDOA2_CTRL_EN3 (offset = 1Eh) [reset = X]
      28. 6.12.28 LDOA3_CTRL_EN1 (offset = 1Fh) [reset = X]
      29. 6.12.29 LDOA3_CTRL_EN2 (offset = 20h) [reset = X]
      30. 6.12.30 LDOA3_CTRL_EN3 (offset = 21h) [reset = X]
      31. 6.12.31 SWB1_CTRL_EN1 (offset = 22h) [reset = X]
      32. 6.12.32 SWB1_CTRL_EN2 (offset = 23h) [reset = X]
      33. 6.12.33 SWB1_CTRL_EN3 (offset = 24h) [reset = X]
      34. 6.12.34 SWB2_LDOA1_CTRL_EN1 (offset = 25h) [reset = X]
      35. 6.12.35 SWB2_LDOA1_CTRL_EN2 (offset = 26h) [reset = X]
      36. 6.12.36 SWB2_LDOA1_CTRL_EN3 (offset = 27h) [reset = X]
      37. 6.12.37 SLP_PIN (offset = 29h) [reset = X]
      38. 6.12.38 OUTPUT_MODE (offset = 2Ah) [reset = X]
      39. 6.12.39 I2C_SLAVE_ADDR (offset = 5Fh) [reset = X]
  8. 7 Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Controller Design Procedure
          1. 7.2.2.1.1 Selecting the Inductor
          2. 7.2.2.1.2 Selecting the Output Capacitors
          3. 7.2.2.1.3 Selecting the FETs
          4. 7.2.2.1.4 Bootstrap Capacitor
          5. 7.2.2.1.5 Setting the Current Limit
          6. 7.2.2.1.6 Selecting the Input Capacitors
        2. 7.2.2.2 Converter Design Procedure
          1. 7.2.2.2.1 Selecting the Inductor
          2. 7.2.2.2.2 Selecting the Output Capacitors
          3. 7.2.2.2.3 Selecting the Input Capacitors
        3. 7.2.2.3 LDO Design Procedure
      3. 7.2.3 Application Curves
      4. 7.2.4 Layout
        1. 7.2.4.1 Layout Guidelines
        2. 7.2.4.2 Layout Example
      5. 7.2.5 VIN 5-V Application
        1. 7.2.5.1 Design Requirements
        2. 7.2.5.2 Design Procedure
        3. 7.2.5.3 Application Curves
    3. 7.3 Power Supply Coupling and Bulk Capacitors
    4. 7.4 Dos and Don'ts
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 第三方产品免责声明
      2. 8.1.2 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 接收文档更新通知
    4. 8.4 支持资源
    5. 8.5 Trademarks
    6. 8.6 静电放电警告
    7. 8.7 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.12.4 BUCK1_CTRL_EN1 (offset = 07h) [reset = X]

Figure 6-78 BUCK1_CTRL_EN1 Register
Bit76543210
Bit NameBUCK1_
LDOA3_
PGM		BUCK1_
LDOA2_
PGM		BUCK1_
SWA1_PGM		BUCK1_
BUCK6_
PGM		BUCK1_
BUCK5_
PGM		BUCK1_
BUCK4_
PGM		BUCK1_
BUCK3_
PGM		BUCK1_
BUCK2_
PGM
TPS6508610000000000
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Table 6-67 BUCK1_CTRL_EN1 Register Descriptions
BitFieldTypeResetDescription
7BUCK1_LDOA3_PGMR/WXLDOA3 PGOOD masked
0: LDOA3 PGOOD is part of Enable Logic.
1: LDOA3 PGOOD is masked and is not part of enable logic.
6BUCK1_LDOA2_PGMR/WXLDOA2 PGOOD masked
0: LDOA2 PGOOD is part of Enable Logic.
1: LDOA2 PGOOD is masked and is not part of enable logic.
5BUCK1_SWA1_PGMR/WXSWA1 PGOOD masked
0: SWA1 PGOOD is part of Enable Logic.
1: SWA1 PGOOD is masked and is not part of enable logic.
4BUCK1_BUCK6_PGMR/WXBUCK6 PGOOD masked
0: BUCK6 PGOOD is part of Enable Logic.
1: BUCK6 PGOOD is masked and is not part of enable logic.
3BUCK1_BUCK5_PGMR/WXBUCK5 PGOOD masked
0: BUCK5 PGOOD is part of Enable Logic.
1: BUCK5 PGOOD is masked and is not part of enable logic.
2BUCK1_BUCK4_PGMR/WXBUCK4 PGOOD masked
0: BUCK4 PGOOD is part of Enable Logic.
1: BUCK4 PGOOD is masked and is not part of enable logic.
1BUCK1_BUCK3_PGMR/WXBUCK3 PGOOD masked
0: BUCK3 PGOOD is part of Enable Logic.
1: BUCK3 PGOOD is masked and is not part of enable logic.
0BUCK1_BUCK2_PGMR/WXBUCK2 PGOOD masked
0: BUCK2 PGOOD is part of Enable Logic.
1: BUCK2 PGOOD is masked and is not part of enable logic.