TIDUEY0A November   2020  – December 2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Li-ion Cell Formation Equipment
    2. 1.2 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 System Design Theory
      1. 2.2.1 Feedback Controller
      2. 2.2.2 DC/DC Start-Up
      3. 2.2.3 High-Resolution PWM Generation
      4. 2.2.4 Output Inductor and Capacitor Selection
      5. 2.2.5 Current and Voltage Feedback
    3. 2.3 Highlighted Products
      1. 2.3.1 TMS320F28P650DK
      2. 2.3.2 ADS9324
      3. 2.3.3 INA630
      4. 2.3.4 UCC27284
      5. 2.3.5 REF50E
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Software
      1. 3.2.1 Opening the Project Inside Code Composer Studio
      2. 3.2.2 Project Structure
      3. 3.2.3 Software Flow Diagram
    3. 3.3 Test Setup
      1. 3.3.1 Hardware Setup to Test Bidirectional Power Flow
      2. 3.3.2 Hardware Setup to Tune the Current and Voltage Loop
      3. 3.3.3 Hardware Setup for Current and Voltage Calibration
      4. 3.3.4 Lab Variables Definitions
      5. 3.3.5 Test Procedure
        1. 3.3.5.1 Lab 1. Open-Loop Current Control Single Phase
          1. 3.3.5.1.1 Setting Software Options for Lab 1
          2. 3.3.5.1.2 Building and Loading the Project and Setting up Debug Environment
          3. 3.3.5.1.3 Running the Code
        2. 3.3.5.2 Lab 2. Closed Loop Current Control Single Channel
          1. 3.3.5.2.1 Setting Software Options for Lab 2
          2. 3.3.5.2.2 Building and Loading the Project and Setting up Debug Environment
          3. 3.3.5.2.3 Run the Code
        3. 3.3.5.3 Lab 3. Open Loop Voltage Control Single Channel
          1. 3.3.5.3.1 Setting Software Options for Lab 3
          2. 3.3.5.3.2 Building and Loading the Project and Setting up Debug Environment
          3. 3.3.5.3.3 Running the Code
        4. 3.3.5.4 Lab 4. Closed Loop Current and Voltage Control Single Channel
          1. 3.3.5.4.1 Setting Software Options for Lab 4
          2. 3.3.5.4.2 Building and Loading the Project and Setting up Debug Environment
          3. 3.3.5.4.3 Running the Code
        5. 3.3.5.5 Lab 5. Closed Loop Current and Voltage Control Four Channels
          1. 3.3.5.5.1 Setting Software Options for Lab 5
          2. 3.3.5.5.2 Building and Loading the Project and Setting up Debug Environment
          3. 3.3.5.5.3 Running the Code
        6. 3.3.5.6 Calibration
    4. 3.4 Test Results
      1. 3.4.1 Current Load Regulation
      2. 3.4.2 Voltage Load Regulation
      3. 3.4.3 Current Linearity Test
      4. 3.4.4 Voltage Loop Linearity Test
      5. 3.4.5 Bidirectional Current Switching Time
      6. 3.4.6 Current Step Response
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author
  12. 6Revision History

3.2.2 Project Structure

Figure 3-3 shows the general structure of the project. Once the project is imported, the Project Explorer appears inside CCS as shown in Figure 3-4.

Note: Figure 3-4 shows the project for F28p65x; however, if a different device is chosen from the page, the structure is similar.
TIDA-010086 Project Structure Overview Figure 3-3 Project Structure Overview

Solution-specific and device-independent files that consist of the core algorithmic code are in .c/h.

Board-specific and device-specific files are in _hal.c/h. This file consists of device-specific drivers to run the solution. If the user wants to use a different modulation scheme or a different device, the user is required only to make changes to these files, besides changing the device support files in the project.

The -main.c file consists of the main framework of the project. This file consists of calls to the board and solution file that help in creating the system framework, along with the interrupt service routines (ISRs) and slow background tasks.

For this design, the solution is bt4ch.

The powerSUITE page can be opened by clicking on the main.syscfg file, listed under the Project Explorer. The page generates the _settings.h file. This file is the only C language-based file used in the compile of the project that is generated by the powerSUITE page. The user must not modify this file manually, because the changes are overwritten by powerSUITE each time the project is saved. The _settings.h file includes function of the operation mode selection and the compensation settings for current and voltage control loop. _user_settings.h is included by the _settings.h and can be used to keep any settings that are outside the scope of powerSUITE tools such as #defines for ADC mapping, GPIOs, and so forth.

The _cal.h file consists of gain and offset values for current and voltage measurements.

The _.ccxml settings up which debugger to use for the reference design. In this design the connection of XDS110 USB debug probe is used and the target device is TMS320F28P65DK9.

The Kit.json and solution.js files are used internally by powerSUITE, and must not be modified by the user. Any changes to these files results in the project not functioning properly.

The solution name is also used as the module name for all the variables and defines used in the solution. Hence, all variables and function calls are prepended by the BT4CH header (for example, BT4CH_userParam_chX). This naming convention lets the user combine different solutions while avoiding naming conflicts.

TIDA-010086 Project Explorer View of the BT4PH Project Figure 3-4 Project Explorer View of the BT4PH Project

The bt4ch project consists of three ISRs (ISR1, ISR2, and ISR3).

  • ISR1 is used to sense the input supply voltage and output capacitor voltage of the buck converters. ISR1 is triggered by ADCC conversion complete and runs at same frequency as the external ADC CONVST. ADCC senses input voltage and output voltage of the converters, and the output is used to implement the soft-start of the DC/DC.
  • ISR2 is triggered by the BUSY signal of the ADS9324. The external ADC is programmed for a 400 kSPS sample rate (CONVST), with oversampling rate (OSR) set to 8 which sets the ISR frequency to 50 kHz.
  • ISR3 is triggered by SPI receive FIFO interrupt. The ISR is used to read the external ADC data from FIFO registers, and run the control loop functions.

Figure 3-6 shows the time taken by ISR1, ISR2, and ISR3 when all four channels are ON. The total time taken three ISRs is less than 6 μs which is less 30% of CPU usage for 50 kSPS control loop sample rate. Figure 3-5 and Figure 3-7 show ISR time for when only one channel is ON and all channels are OFF.

TIDA-010086 ISR Execution Time for One Channel Figure 3-5 ISR Execution Time for One Channel
TIDA-010086 ISR Execution Time for Four Channels Figure 3-6 ISR Execution Time for Four Channels
TIDA-010086 ISR Execution Time When All Channels are OFF Figure 3-7 ISR Execution Time When All Channels are OFF