SPRUIY5A February   2021  – July 2021 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

 

  1.   Trademarks
  2. 1 Stackup
  3. 2 Floorplan Component Placement
  4. 3 Critical Interfaces Impact Placement
  5. 4 Route Critical Interfaces First
  6. 5 Route SERDES Interfaces First
  7. 6 Route DDR Signals
    1. 6.1 Address, Command, Control, and Clock Group Routes
    2. 6.2 Data Group Routes
  8. 7 Complete Power Decoupling
  9. 8 Route Lowest Priority Interfaces
  10. 9 References
  11. 10Revision History

5 Route SERDES Interfaces First

The previous section highlighted priorities for the PCB routing. The BGA ball map is also arranged to support routing the highest priority interfaces first. You will notice that most of the PCIe/USB3 SERDES interfaces are located on the outer two rings. The transmit pair should be routed away from the SoC on the top layer leaving a gap without blocking vias. The receive pair requires vias to escape as a differential pair on the bottom or on an interior layer. For the routing of the serdes signals on the AM64x EVM on the top layer and on the SIG2 layer, see Figure 5-1. Wide traces can limit the signal loss, but complicate the impedance requirements, which must be met.

Figure 5-1 Serdes Escapes