The images above show the data group routing for the DDR4 memory. Note that the PCB layout designer grouped all 11 nets for each byte group on a single layer. This is not a requirement but it is strongly recommended as this simplifies the signal length and delay matching requirements.

The DDR4 design for the AM64x GP EVM includes a single 16-bit device for a 16bit data bus. The order of the byte lane connection is determined by the order of the byte lane signals on the AM64x. The routing layers shown in the picture above including the top, the bottom, the SIG1 layer and the SIG2 layer.

Figure 6-5 shows escape of the signals from the BGA of the AM64x. Note that most of the routing is on the internal layers SIG1 and SIG2. All of the DDR signals are connected directly to a via within the BGA footprint. Signals travel through traces routed on the top and bottom layers at a different speed then traces routed on internal layers. This difference must be included in the length matching calculations. Ideally, all DDR4 signals should be routed on internal layers. A second via next to the pads on the DDR4 memory is used to connect to the memory device. Each trace has only two vias.