The address, command, and clock signals are routed directly to the memory device followed by the VTT termination resistors. The VTT termination is placed at the end of the trace past the connection to the memory. If 8-bit memories are used, the address, command and clock signals should be in a fly-by manner.

The bottom, SIG1 and SIG2 layers are used to escape and route the address and command signals. The traces must be length matched to ensure that the signals arrive at the memory at the same time. Length matching must be from the SoC to memory pin individually including the stub to the memory pad. The trace connection to the VTT termination resistor is not included in this measurement.

The escapes of the address and command signals on these three layers are shown above. Details of the escape are shown in Figure 6-4.

Address signals were routed directly from the SoC to the via next to the associated pad for the memory device. This requires that the address signals escape in the correct order. Some of the signals are routed looped around pins closer to the center of the AM64x to achieve the correct order. Using a third steering via in the trace simplifies the escape but complicates the length matching calculation. It is always best to have the same number of vias for each of the address and command signals.

Placing the address pins of the memory closer to the AM64x allows the address and command signals to be routed without crossing a byte data lane.