SPRADS1 June   2025 F29H850TU

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Hardware Security Module
    2. 1.2 Flash Programming Fundamentals
    3. 1.3 High-Level Flow
    4. 1.4 Flow Chart
  5. 2Flash-Based UART SBL with FOTA
    1. 2.1 Implementation
    2. 2.2 Triggering a Bank Swap
  6. 3FOTA_Example_Application
    1. 3.1 led_blinky_cpu1.c
    2. 3.2 Combining the Flash-Based SBL with the FOTA_Example_Application
    3. 3.3 Adding a CPU3 Application
  7. 4Host Application: UART Flash Programmer
    1. 4.1 Overview
  8. 5Example Usage
    1. 5.1 Loading the SBL onto the Device
      1. 5.1.1 Loading by CCS (JTAG)
      2. 5.1.2 Loading via UART Boot and the UART Flash Kernel
    2. 5.2 Example UART Loading Process
  9. 6FAQ
    1. 6.1 General
    2. 6.2 Application Load
  10. 7Summary
  11. 8References

2.1 Implementation

As stated above, the primary purpose of the flash-based UART SBL with FOTA project is to provide an example implementation for flash-based firmware upgrades. The implementation has a lot in common with the ex3_uart_flash_kernel project (F29h85x_sdk_xx_xx_xx_xx\examples\driverlib\single_core\flash\uart_flash_kernel), so TI recommends to review the Serial Flash Programming of F29H85x™ application note describing the ex3_uart_flash_kernel project. The application note provides more context on how the flash-based SBL can be programmed to both an HS-FS and HS-SE device over UART.

A key difference between the UART flash kernel implementation and the flash-based SBL is that the SBL does not need to be loaded in by bootROM after every reset. Once the project is loaded to CPU1 flash (either by CCS or the UART flash kernel), the flash boot mode can be used to enter the SBL. The SBL occupies the first 83KB of CPU1 flash memory beginning at 0x10001000. The sample application provided in the FOTA_Example_Application project is stored at 0x10020000 and is separate from the SBL. The location of the sample application can be changed as needed, but make sure to update both the linker file of the SBL and the example application. For more details about this, refer to Section 3.2.

Another key difference in the flash-based SBL project is that the bank swapping mechanism is used to swap between firmware images. Thus, the F29H85x must be in bank mode 1 or bank mode 3 (0 and 2 do not support bank swapping). If only CPU1 is running, then use bank mode 1. If both CPU1 and CPU3 are executing an application, then use bank mode 3. Refer to the TRM and data sheet for more details about how flash memory is distributed based on bank mode. To program bank mode 1 or 3 on the F29H85x, use the flash plugin in CCS or the flash API function (Fapi_issueProgBankMode()). To do so in CCS, refer to Section 5.1.1. After programming the bank mode, this takes effect after a device reset.

Once the flash-based SBL has been programmed and is executing in CPU1 flash, this is ready to receive commands from the Host Application. More details about the host application can be found in Section 4. A demonstration of using the project can be found in Section 5.