SPRADS1 June   2025 F29H850TU

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Hardware Security Module
    2. 1.2 Flash Programming Fundamentals
    3. 1.3 High-Level Flow
    4. 1.4 Flow Chart
  5. 2Flash-Based UART SBL with FOTA
    1. 2.1 Implementation
    2. 2.2 Triggering a Bank Swap
  6. 3FOTA_Example_Application
    1. 3.1 led_blinky_cpu1.c
    2. 3.2 Combining the Flash-Based SBL with the FOTA_Example_Application
    3. 3.3 Adding a CPU3 Application
  7. 4Host Application: UART Flash Programmer
    1. 4.1 Overview
  8. 5Example Usage
    1. 5.1 Loading the SBL onto the Device
      1. 5.1.1 Loading by CCS (JTAG)
      2. 5.1.2 Loading via UART Boot and the UART Flash Kernel
    2. 5.2 Example UART Loading Process
  9. 6FAQ
    1. 6.1 General
    2. 6.2 Application Load
  10. 7Summary
  11. 8References

5.2 Example UART Loading Process

  • Verify the device is in bank mode 0
SSU_GEN_REG.BANKMODE Showing Bank Mode 0 Figure 5-2 SSU_GEN_REG.BANKMODE Showing Bank Mode 0
  • Put the device in UART Boot Mode (GPIO 72 -> 0 and GPIO 84 -> 1)
  • Trigger a device reset
  • Send the kernel with uart_flash_programmer.exe
    1. .\uart_flash_programmer.exe -d f29h85x -p COM89 -k .\ex3_uart_flash_kernel.cert.bin -a1 .\flash_based_uart_sbl_with_fota.bin
  • The kernel is running at this point
Host Output After Sending Kernel Figure 5-3 Host Output After Sending Kernel
  • Can verify that the kernel is running by connecting to CPU1 and observing that the PC is in LPAx RAM
Kernel Running in RAM Figure 5-4 Kernel Running in RAM
  • Resume kernel execution
  • Send DFU CPU1 command to download the flash-based SBL
Host Output of DFU CPU1 Command Figure 5-5 Host Output of DFU CPU1 Command
  • Connect to CPU1 and program bank mode 1
  • Configure flash boot mode (GPIO 72 -> 1 GPIO 84 -> 1)
  • Trigger a device reset
  • Can verify that flash-based SBL is now running by connecting to CPU1 and seeing that the PC is running in flash
Device Successfully Boots to Flash Figure 5-6 Device Successfully Boots to Flash
  • Program flash-based SBL to the inactive region of flash by sending the DFU CPU1 command
Host Programmer Output of DFU CPU1 Command Figure 5-7 Host Programmer Output of DFU CPU1 Command
  • Can verify that flash-based SBL is programmed to the inactive flash region with the memory browser
FLC1.B2 and FLC1.B3 After Firmware Programmed to Inactive Flash Region Figure 5-8 FLC1.B2 and FLC1.B3 After Firmware Programmed to Inactive Flash Region

At this point, the flash-based SBL and FOTA_Example_Application have been programmed to both the active and inactive regions of CPU1 flash memory.