SPRACT3A September   2020  – June 2026 F29H850TU , F29H859TU-Q1 , F29P329SM-Q1 , TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P550SG , TMS320F28P550SJ , TMS320F28P559SG-Q1 , TMS320F28P559SJ-Q1 , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Secure Flash Boot Overview
  6. 3 CMAC Authentication
  7. 4 Secure Flash Boot Options
  8. 5 Secure Flash Boot Flow
  9. 6 C2000Ware Example Details
  10. 7 Authenticating Flash Code Beyond 16 KB
  11. 8 Debug Resources
  12. 9 Additional Information and Points to Consider
  13. 10Alignment of C2000 CMAC Algorithm to OpenSSL
    1. 10.1 C28x Memory and Binary File Byte Ordering
    2. 10.2 Flash Binary Byte Ordering
    3. 10.3 CMAC Key Byte Ordering
    4. 10.4 CMAC Output Alignment Procedure
    5. 10.5 Worked Example
    6. 10.6 Summary of Differences
  14. 11References
  15. 12Revision History

8 Debug Resources

Table 8-1 Secure Flash Boot Debug Scenarios
Scenario Behavior
Failed Secure boot in CPU1

Standalone Boot: Device is reset.

Emulation Boot: CPU1 halts inside the address range 0x3FB13C – 0x3FB142
Failed Secure boot in CPU2

Bit21 of the CPU2TOCPU1IPCBOOTSTS (1) register will be set.

CPU2 sends IPC command to CPU1 with secure flash CMAC error code.
Failed Secure boot in CM

Bit21 of the CMTOCPU1IPCBOOTSTS (2) register will be set. CM

sendsIPC command to CPU1 with secure flash CMAC error code.
Has a successful Secure boot run for CPU1?

Bits7:0 of the CPU1 BootROM status residing in the 0x0000 0002address location will reflect 0x3.
Has a successful Secure boot run for CPU2?

Bits7:0 of the CPU2TOCPU1IPCBOOTSTS (1) register will reflect 0x3.
Has a successful Secure boot run for CM?

Bits7:0 of the CMTOCPU1IPCBOOTSTS (2) register will reflect 0x3.
  1. Same information is also captured in the 0x0000 0002 address location of CPU2.
  2. Same information is also captured in the 0x2000 0000 address location of CM.