SNLU273 December   2020 DS160PR810

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Features
    2. 1.2 Applications
  3. 2Description
    1. 2.1  DS160PR810 4-Level I/O Control Inputs
    2. 2.2  DS160PR810 Modes of Operation
    3. 2.3  DS160PR810 SMBus or I2C Register Control Interface
    4. 2.4  DS160PR810 Equalization Control
    5. 2.5  DS160PR810 RX Detect State Machine
    6. 2.6  DS160PR810 DC Gain Control
    7. 2.7  DS160PR810 EVM Global Controls
    8. 2.8  DS160PR810EVM Downstream Devices Control
    9. 2.9  DS160PR810EVM Upstream Devices Control
    10. 2.10 Quick-Start Guide (Pin Mode)
    11. 2.11 Quick-Start Guide (SMBus Slave Mode)
  4. 3Test Setup and Results
  5. 4Schematics
  6. 5Board Layout
  7. 6Bill of Materials
  8. 7References

2.7 DS160PR810 EVM Global Controls

Table 2-7 shows DS160PR810EVM-RSC global controls that affect all devices on the board.

Table 2-7 EVM Global Controls
COMPONENTNAMEFUNCTION / DESCRIPTION
J1

3x2 Header

MODE control tied to MODE pins of all four DS160PR810 devices on the EVM


L0: All devices set to Pin Mode (Default)
L1: All devices set to SMBus, I2C Maseter Mode


L2: SMBus, I2C Slave Mode
L3: Reserved

J2

3x2 Header

RX DET control tied to RX DET pins of all four DS160PR810 devices on the EVM


L0: RX Detect state machine disabled on all devices


L1: RX Detect state machine enabled on all devices (3 valid detections needed)


L2: RX Detect state machine enabled on all devices (2 valid detections needed)


L3: RX Detect state machine enabled on all devices (1 valid detection needed) - Default

J3

5x2 Header

SMBus, I2C interface. All four DS160PR810 devices on the EVM are on the same bus and can be accessed through this interface.

J4

3x1 Header

PWDN control tied to PD1 and PD2 pins of all four DS160PR810 devices on the EVM PWDN tied to GND: All devices enabled (Default) PWDN tied to 3.3V_REG: All devices disabled.

PWDN floating: Tie PCIe system PRSNT signal to PWDN using J6 for the PWDN control (optional for PCIe use case)

J53x1 HeaderAccess point to the WP (write protect) pin of the onboard EEPROM devices WP tied to GND: I2C Access to the EEPROM enabled WP floating: I2C Access to the EEPROM disabled (default)
J6

2x1 Header

Alternative PWDN Control PWDN floating: Use J3 for the PWDN control PWDN tied to PRSNT: PRSNT signal controls PWDN (optional for PCIe use case)
J7, J8, J9, J10

3x1 Headers

PCIe PRSNT Signal Controls Tie pins 1-2 on J7, J8, J9, and J10: Allow support any PCIe bus width (default) Tie pins 2-3 of J7, leave J8, J9, and J10 floating: Force x1 PCIe bus width Tie pins 2-3 of J8, leave J7, J9, and J10 floating: Force x4 PCIe bus width Tie pins 2-3 of J9, leave J7, J8, and J10 floating: Force x8 PCIe bus width Tie pins 2-3 of J10, leave J7, J8, and J9 floating: Force x16 PCIe bus width
J11

2x1 Header

Onboard regulator input. Apply 12 V when using the EVM as a standalone system. DO NOT APPLY power if plugging the EVM into a system as the power is provided through the gold finger connector (CONN1).
J12

2x1 Header

Access point to the GND reference
J13

2x1 Header

Onboard 3.3-V output