SNLU273 December   2020 DS160PR810

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Features
    2. 1.2 Applications
  3. 2Description
    1. 2.1  DS160PR810 4-Level I/O Control Inputs
    2. 2.2  DS160PR810 Modes of Operation
    3. 2.3  DS160PR810 SMBus or I2C Register Control Interface
    4. 2.4  DS160PR810 Equalization Control
    5. 2.5  DS160PR810 RX Detect State Machine
    6. 2.6  DS160PR810 DC Gain Control
    7. 2.7  DS160PR810 EVM Global Controls
    8. 2.8  DS160PR810EVM Downstream Devices Control
    9. 2.9  DS160PR810EVM Upstream Devices Control
    10. 2.10 Quick-Start Guide (Pin Mode)
    11. 2.11 Quick-Start Guide (SMBus Slave Mode)
  4. 3Test Setup and Results
  5. 4Schematics
  6. 5Board Layout
  7. 6Bill of Materials
  8. 7References

2.8 DS160PR810EVM Downstream Devices Control

Table 2-8 shows the DS160PR810EVM downstream device controls that affect DS1 and DS2 devices on the board.

Table 2-8 EVM Downstream Devices Controls
COMPONENTNAMEFUNCTION / DESCRIPTION
J14

3x2 Header

Gain Controls tied to GAIN pins of all downstream device banks
L0: –6 dB Gain Setting
L1: –3 dB Gain Setting
L2: 3 dB Gain Setting
L3: 0 dB Gain Setting (default)
J1512x2 Header

Pin Mode: EQ1 controls for each downstream device and device bank.

Use pins 1–6 for configuring EQ1_0 pin of Bank 0 of DS1 device.

Use pins 7–12 for configuring EQ1_1 pin of Bank 1 of DS1 device.

Use pins 13–18 for configuring EQ1_0 pin of Bank 0 of DS2 device.

Use pins 19–24 for configuring EQ1_1 pin of Bank 1 of DS2 device.

SMBus, I2C Modes: ADDR1 controls for each downstream device.

Use pins 1–6 for configuring ADDR1 pin of DS1 device.

Use pins 13–18 for configuring ADDR1 pin of DS2 device.

Install a shunt to achieve L0, L1, or L2 level on the pin. Leave floating to achieve L3 level on the pin.

J1612x2 Header

Pin Mode: EQ0 controls for each downstream device and device bank.

Use pins 1–6 for configuring EQ0_0 pin of Bank 0 of DS1 device.

Use pins 7–12 for configuring EQ0_1 pin of Bank 1 of DS1 device.

Use pins 13–18 for configuring EQ0_0 pin of Bank 0 of DS2 device.

Use pins 19–24 for configuring EQ0_1 pin of Bank 1 of DS2 device.

SMBus, I2C Modes: ADDR0 controls for each downstream device.

Use pins 1–6 for configuring ADDR0 pin of DS1 device.

Use pins 13–18 for configuring ADDR0 pin of DS2 device.

Install a shunt to achieve L0, L1, or L2 level on the pin. Leave floating to achieve L3 level on the pin.

J17

3x1 Header

GAIN / SDA Dual Function Pin Provision for DS1 Device Install shunt across pins 1-2 for operation in Pin Mode (default) Install shunt across pins 2-3 for operation in SMBus, I2C Modes
J183x1 HeaderRX DET / SCL Dual Function Pin Provision for DS1 Device Install shunt across pins 1-2 for operation in Pin Mode (default) Install shunt across pins 2-3 for operation in SMBus, I2C Modes
J193x1 HeaderGAIN / SDA Dual Function Pin Provision for DS2 Device Install shunt across pins 1-2 for operation in Pin Mode (default) Install shunt across pins 2-3 for operation in SMBus, I2C Modes

J20

3x1 Header

RX DET / SCL Dual Function Pin Provision for DS2 Device Install shunt across pins 1-2 for operation in Pin Mode (default) Install shunt across pins 2-3 for operation in SMBus, I2C Modes