SNAU252 June   2020 LMK04832-SP

 

  1.   LMK04832EVM-CVAL User’s Guide
    1.     Trademarks
    2. 1  Evaluation Board Kit Contents
    3. 2  Quick Start
      1. 2.1 Quick Start Description
        1. 2.1.1 Clock Outputs Page Description
        2. 2.1.2 TICS Pro Tips
    4. 3  PLL Loop Filters and Loop Parameters
      1. 3.1 PLL1 Loop Filter
      2. 3.2 PLL2 Loop Filter
    5. 4  Default TICS Pro Mode
    6. 5  Using TICS Pro to Program the LMK04832-SP
      1. 5.1 Start TICS Pro Application
      2. 5.2 Select Device
      3. 5.3 Program the Device
      4. 5.4 Restoring a Default Mode
      5. 5.5 Visual Confirmation of Frequency Lock
      6. 5.6 Enable Clock Outputs
    7. 6  Evaluation Board Inputs and Outputs
    8. 7  Recommended Test Equipment
    9. 8  Length Matching
    10. 9  Schematics
    11. 10 Bill of Materials
  2.   A TICS Pro Usage
    1.     A.1 Communication Setup
    2.     A.2 User Controls
    3.     A.3 Raw Registers Page
    4.     A.4 Set Modes Page
    5.     A.5 Holdover Page
    6.     A.6 CLKinX Control Page
    7.     A.7 PLL1 and 2 Page
    8.     A.8 SYNC / SYSREF Page
    9.     A.9 Clock Outputs Page
    10.     A.10 Other Page
    11.     A.11 Current Calculator Page
    12.     A.12 Burst Page

3.1 PLL1 Loop Filter

Table 2. PLL1 Loop Filter Parameters for Crystek 122.88-MHz VCXO(1)

122.88-MHz VCXO PLL
Phase Margin 50˚ Kφ (Charge Pump) 450 µA
Loop Bandwidth 14 Hz Phase Detector Freq 1.024 MHz
VCO Gain 2.5 kHz/V
Reference Clock Frequency 122.88 MHz Output Frequency 122.88 MHz
(To PLL 2)
Loop Filter Components LF1_C1 (C75) = 100 nF LF1_C2 (C73) = 680 nF LF1_R2 (R64) = 39 kΩ
(1) Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφ and N will change the loop bandwidth.