SNAU252 June   2020 LMK04832-SP

 

  1.   LMK04832EVM-CVAL User’s Guide
    1.     Trademarks
    2. 1  Evaluation Board Kit Contents
    3. 2  Quick Start
      1. 2.1 Quick Start Description
        1. 2.1.1 Clock Outputs Page Description
        2. 2.1.2 TICS Pro Tips
    4. 3  PLL Loop Filters and Loop Parameters
      1. 3.1 PLL1 Loop Filter
      2. 3.2 PLL2 Loop Filter
    5. 4  Default TICS Pro Mode
    6. 5  Using TICS Pro to Program the LMK04832-SP
      1. 5.1 Start TICS Pro Application
      2. 5.2 Select Device
      3. 5.3 Program the Device
      4. 5.4 Restoring a Default Mode
      5. 5.5 Visual Confirmation of Frequency Lock
      6. 5.6 Enable Clock Outputs
    7. 6  Evaluation Board Inputs and Outputs
    8. 7  Recommended Test Equipment
    9. 8  Length Matching
    10. 9  Schematics
    11. 10 Bill of Materials
  2.   A TICS Pro Usage
    1.     A.1 Communication Setup
    2.     A.2 User Controls
    3.     A.3 Raw Registers Page
    4.     A.4 Set Modes Page
    5.     A.5 Holdover Page
    6.     A.6 CLKinX Control Page
    7.     A.7 PLL1 and 2 Page
    8.     A.8 SYNC / SYSREF Page
    9.     A.9 Clock Outputs Page
    10.     A.10 Other Page
    11.     A.11 Current Calculator Page
    12.     A.12 Burst Page

3 PLL Loop Filters and Loop Parameters

In jitter cleaning applications that use a cascaded or dual PLL architecture, the first PLL’s purpose is to substitute the phase noise of a low-noise oscillator (VCXO) for the phase noise of a dirty reference clock. The first PLL is typically configured with a narrow loop bandwidth to minimize the impact of the reference clock phase noise. The reference clock consequently serves only as a frequency reference rather than a phase reference.

The loop filters on the LMK04832EVM-CVAL evaluation board are setup using the approach above. The loop filter for PLL1 has been configured for a narrow loop bandwidth (< 1 kHz). The specific loop bandwidth values depend on the phase noise performance of the oscillator mounted on the board. Table 2 and Table 3 contain the parameters for PLL1 and PLL2 for each oscillator option.

TI’s PLLatinum™ Sim tool can be used to optimize PLL phase noise/jitter for given specifications. See http://www.ti.com/tool/pllatinumsim-sw for more information.