Single tone 3.5-GHz transmit output signal of Channel A is monitored using R&S Phase noise analyzer to see implication on ripple and noise coupling from supply rail into signal chain. Internal charge pump current is set to default 1 mA for this test. Charge pump current sets the PLL loop bandwidth, changing the charge current results into changes into PLL loop bandwidth response. Lower values of charge current reduces loop bandwidth of PLL improving rejection at higher frequency. PSMR plot 1.8-V as shown in Figure 2-4 gives relation of overall PLL loop bandwidth response to external supply rail for 1-mA charge pump current. As we see in Figure 3-1 the integrated noise up to 100-MHz bandwidth is -51.7 dBc.

The phase noise plot starts close to -95 dBc at 100-Hz offset which clearly implies that ripple and noise injected from supply post LC filtering is close to noise floor. TPS62913 ultra low noise DC-DC (16.8 uV RMS) powering 1.8-V PLL enables to achieves performance similar to Low Noise LDO powered solution.