SLVAF10 March   2021 TPS1H000-Q1 , TPS1H100-Q1 , TPS1H200A-Q1 , TPS1HA08-Q1 , TPS1HB08-Q1 , TPS1HB16-Q1 , TPS1HB35-Q1 , TPS1HB50-Q1 , TPS2H000-Q1 , TPS2H160-Q1 , TPS2HB16-Q1 , TPS2HB35-Q1 , TPS2HB50-Q1 , TPS4H000-Q1 , TPS4H160-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Device Thermals
  4. 3Timing Limitations
    1. 3.1 Background
    2. 3.2 Pulse-Width distortion (PWD)
      1. 3.2.1 Timing Impact of Delay Mismatch
      2. 3.2.2 Power Impact of Delay Mismatch on Resistive Loads
    3. 3.3 Finite Slew Rate
      1. 3.3.1 Timing Impact of Finite Slew Rate and Slew Rate Mismatch
      2. 3.3.2 Impact of Finite Slew Rate on Resistive Load Power
      3. 3.3.3 Impact of Slew Rate on LED Power
  5. 4System-Level Considerations
    1. 4.1 Diagnostics and Protection
      1. 4.1.1 Analog Current Sense
    2. 4.2 Dimming Ratio
    3. 4.3 Side-Stepping Frequency Limitations
  6. 5References

4.3 Side-Stepping Frequency Limitations

In some applications, systems may need to operate at PWM frequencies beyond the 1-2 kHz which most HSS are limited to, but still maintain the robust diagnostics and protection features of a high side switch.

This can be accomplished by reassigning the PWM switching duties from the HSS to a separate low-side switch, such as ULN2003A, which is capable of much higher-frequency operation. For higher-current applications, N-ch FET based low-side driver such as DRV103 may be used. This topology is shown in Figure 4-3. With this dual-IC strategy, a designer still must consider frequency dependent power dissipation and thermals in the HSS, but not HSS switching losses.

GUID-30981A52-48EC-4869-8051-8CB966887324-low.png Figure 4-3 Dual-Driver Strategy for High Frequency PWM