SLVAF10 March   2021 TPS1H000-Q1 , TPS1H100-Q1 , TPS1H200A-Q1 , TPS1HA08-Q1 , TPS1HB08-Q1 , TPS1HB16-Q1 , TPS1HB35-Q1 , TPS1HB50-Q1 , TPS2H000-Q1 , TPS2H160-Q1 , TPS2HB16-Q1 , TPS2HB35-Q1 , TPS2HB50-Q1 , TPS4H000-Q1 , TPS4H160-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Device Thermals
  4. 3Timing Limitations
    1. 3.1 Background
    2. 3.2 Pulse-Width distortion (PWD)
      1. 3.2.1 Timing Impact of Delay Mismatch
      2. 3.2.2 Power Impact of Delay Mismatch on Resistive Loads
    3. 3.3 Finite Slew Rate
      1. 3.3.1 Timing Impact of Finite Slew Rate and Slew Rate Mismatch
      2. 3.3.2 Impact of Finite Slew Rate on Resistive Load Power
      3. 3.3.3 Impact of Slew Rate on LED Power
  5. 4System-Level Considerations
    1. 4.1 Diagnostics and Protection
      1. 4.1.1 Analog Current Sense
    2. 4.2 Dimming Ratio
    3. 4.3 Side-Stepping Frequency Limitations
  6. 5References

3.3.1 Timing Impact of Finite Slew Rate and Slew Rate Mismatch

If slew rate on/off matching is provided in the data sheet, as it is for TPS1H100-Q1, we can consider the worst-case impact on pulse width from both propagation delay mismatch and slew-rate mismatch. If we consider pulse-width as the duration from the rising and falling edges taken at 50% of max value we get:

Equation 24. GUID-8380716A-0BFB-4F9D-8D6D-7094D603D792-low.png
Equation 25. GUID-395FBFF0-3C6E-40B3-9DBB-B8EDEE49C9AD-low.png
Equation 26. GUID-737EB800-7A45-4736-AF49-FFE9CEBD04F3-low.png

where SRmatch could be positive or negative. If we consider both slew-rate and propagation-delay mismatch, the output pulse-width expression follows:

Equation 27. GUID-43B2D44E-985E-4A5C-8A2A-84613251CB49-low.png

To illustrate the effect, we use specification of TPS1H100-Q1 and Equation 24 to understand the slew-rate mismatch relationship with PWM accuracy.

  • HSS supply voltage: Vvs=10 V and 40 V
  • Pulse-width distortion: td(PWD) = ±50 μs (TPS1H100 min/max spec)
  • ON Slew rate: SRON = 0.36 V/μs
  • Slew rate matching: SRmatch = 0.15 V/μs
  • Duty cycle: DIN = 50%
GUID-0FF21758-3408-4D80-92A4-E97667608322-low.png Figure 3-7 Input-to-Output PW Accuracy Over Supply Voltage, Considering Slew Rate and Delay Mismatch

Clearly, if we consider both PWD and slew rate mismatch this places additional limits on feasible PWM frequency especially at higher supply voltages. It is important to note that each high side switch can have varying switching characteristics. Refer to the device parameters and calculation methods above to determine if a specific set of PWM loading conditions is feasible for a selected high side switch.