SLAU298A November   2009  – May 2021

 

  1.   Trademarks
  2. 1ADS8555EVM-PDK Overview
    1. 1.1 ADS8555EVM-PDK Features
    2. 1.2 ADS8555EVM Features
  3. 2EVM Analog Interface
    1. 2.1 ADC Supply, Input, Voltage Reference, and Digital Connections
    2. 2.2 ADC Amplifier Drive
  4. 3Digital Interface
    1. 3.1 Parallel Interface
    2. 3.2 Serial Interface (SPI)
    3. 3.3 I2C Bus and EEPROM
    4. 3.4 Connections to the PHI Connector
  5. 4Power Supplies
    1. 4.1 External Power Connections and Test Points
    2. 4.2 Low-Dropout Regulator (TPS7A3001 for HVSS)
    3. 4.3 Low-Dropout Regulator (TPS7A4700 for AVDD, HVDD)
  6. 5Installing the ADS8555EVM Software
  7. 6ADS8555EVM Operation
    1. 6.1 Connecting the Hardware and Running the GUI
    2. 6.2 Jumper Settings for the ADS8555EVM
    3. 6.3 Modifying Hardware and Using Software to Evaluate Other Devices in the Family
    4. 6.4 EVM GUI Global Settings for ADC Control and Registers
    5. 6.5 Time Domain Display
    6. 6.6 Frequency Domain Display
    7. 6.7 Histogram Display
  8. 7Bill of Materials, Layout, and Schematics
    1. 7.1 Bill of Materials
    2. 7.2 Board Layout
    3. 7.3 Schematics
  9. 8Revision History

3.2 Serial Interface (SPI)

The ADS8555 ADC uses SPI serial communication in mode 1 (CPOL = 0 and CPHA= 1). Because the serial clock (SCLK) frequency can be as fast as 36 MHz, the ADS8555EVM offers 47-Ω resistors between the controller and device to aid with signal integrity. Typically, in high-speed SPI communication, fast signal edges can cause overshoot; these 47-Ω resistors slow down the signal edges in order to minimize signal overshoot.