SLAU298A November   2009  – May 2021

 

  1.   Trademarks
  2. 1ADS8555EVM-PDK Overview
    1. 1.1 ADS8555EVM-PDK Features
    2. 1.2 ADS8555EVM Features
  3. 2EVM Analog Interface
    1. 2.1 ADC Supply, Input, Voltage Reference, and Digital Connections
    2. 2.2 ADC Amplifier Drive
  4. 3Digital Interface
    1. 3.1 Parallel Interface
    2. 3.2 Serial Interface (SPI)
    3. 3.3 I2C Bus and EEPROM
    4. 3.4 Connections to the PHI Connector
  5. 4Power Supplies
    1. 4.1 External Power Connections and Test Points
    2. 4.2 Low-Dropout Regulator (TPS7A3001 for HVSS)
    3. 4.3 Low-Dropout Regulator (TPS7A4700 for AVDD, HVDD)
  6. 5Installing the ADS8555EVM Software
  7. 6ADS8555EVM Operation
    1. 6.1 Connecting the Hardware and Running the GUI
    2. 6.2 Jumper Settings for the ADS8555EVM
    3. 6.3 Modifying Hardware and Using Software to Evaluate Other Devices in the Family
    4. 6.4 EVM GUI Global Settings for ADC Control and Registers
    5. 6.5 Time Domain Display
    6. 6.6 Frequency Domain Display
    7. 6.7 Histogram Display
  8. 7Bill of Materials, Layout, and Schematics
    1. 7.1 Bill of Materials
    2. 7.2 Board Layout
    3. 7.3 Schematics
  9. 8Revision History

1.2 ADS8555EVM Features

  • Six input channels connected to external single-ended signals that are source applied to subminiature version A (SMA) connectors or headers.
  • Serial and parallel interface connects to the PHI controller via a 60-pin connector (J2).
  • High-voltage power supplies (HVDD and HVSS) are not included. Connect common lab supplies via screw terminal J1.
  • Analog low-voltage supplies (AVDD = 5 V) are generated using an external 15-V supply and a low-dropout regulator (LDO). HVDD (12-V supply) is also generated using the 15-V supply and an LDO. HVSS (–12-V supply) is generated using the –15-V supply and an LDO.
  • Digital low-voltage supply (DVDD = 3.3 V) is generated using USB power from the PHI controller.
  • Integrated or external voltage reference options are available.