SDAA451 July   2026 ADS131M08

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2What is phase shift and phase error?
  6. 3How to calibrate out phase error with the ADS131M08
    1. 3.1 Determining the phase error
    2. 3.2 Converting to the time domain
    3. 3.3 Converting to modulator clock cycles
    4. 3.4 Converting to binary and writing to the PHASEn[9:0] bits
    5. 3.5 Phase calibration considerations
    6. 3.6 Summarizing the phase calibration process
    7. 3.7 Using the Phase Calibration Feature
      1. 3.7.1 Phase calibration considerations examples
  7. 4Synchronizing the ADS131M0x
    1. 4.1 The SYNC/RESET pin on the ADS131M0x
    2. 4.2 The importance of routing the clock signal
      1. 4.2.1 Single Clock Buffer
      2. 4.2.2 Multiple Clock Buffers
  8. 5Summary
  9. 6References

4 Synchronizing the ADS131M0x

Phase error can originate from measurement hardware including the ADC when multiple unsynchronized ADCs are used. For example, multi-string solar installations that need higher channel counts require multiple ADS131M08 devices in parallel.

Systems using multiple ADS131M08 devices require ADC synchronization before data collection. Synchronization establishes a common time reference that ensures all ADCs begin conversions simultaneously. This enables accurate phase comparison across channels of different devices. Without synchronization, each device may begin its conversion cycle at an arbitrary time relative to the others, even when sharing the same clock source. This creates an unknown phase shift between devices that calibration cannot reliably compensate. Figure 4-1 shows a re-creation of the DRDY signals of two ADS131M08 devices sharing the same external clock without synchronization. Note the delay between the falling edges of the signals without synchronization.

DRDY signals between two ADS131M0x with same external clock and without synchronizationFigure 4-1 DRDY signals between two ADS131M0x with same external clock and without synchronization