SDAA451 July   2026 ADS131M08

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2What is phase shift and phase error?
  6. 3How to calibrate out phase error with the ADS131M08
    1. 3.1 Determining the phase error
    2. 3.2 Converting to the time domain
    3. 3.3 Converting to modulator clock cycles
    4. 3.4 Converting to binary and writing to the PHASEn[9:0] bits
    5. 3.5 Phase calibration considerations
    6. 3.6 Summarizing the phase calibration process
    7. 3.7 Using the Phase Calibration Feature
      1. 3.7.1 Phase calibration considerations examples
  7. 4Synchronizing the ADS131M0x
    1. 4.1 The SYNC/RESET pin on the ADS131M0x
    2. 4.2 The importance of routing the clock signal
      1. 4.2.1 Single Clock Buffer
      2. 4.2.2 Multiple Clock Buffers
  8. 5Summary
  9. 6References

3.3 Converting to modulator clock cycles

Write the phase compensation value to the PHASEn[9:0] register as a binary representation of the required modulator clock periods tMOD. Use Equation 10 to calculate tMOD and Equation 11 to calculate the modulator frequency fMOD.

Equation 15. 10tMOD=1fMOD
Equation 16. 11fMOD=fCLK2

Where:

  • fCLK is the master clock frequency (usually 8.192 MHz in the ADS131M08 for high resolution mode)
  • fMOD is the modulator clock frequency
  • tMOD is the modulator clock period

Equation 12 determines the number of modulator clock cycles using the time delay from the CT, ∆t and tMOD:

Equation 17. 12N=∆ttMOD

Where:

  • N is the number of modulator clock cycles that should be written to the PHASEn[9:0] bits in the CHn_CFG register
  • Δt is the time delay in seconds from the CT
  • tMOD is the modulator clock period

Using the class 0.2 CT time shift of 9.28µs and combining Equations 10, 11, and 12 results in a phase delay equivalent to 38 tMOD:

Equation 18. 13N=9.28μs(28.192MHz)=38