SDAA451 July   2026 ADS131M08

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2What is phase shift and phase error?
  6. 3How to calibrate out phase error with the ADS131M08
    1. 3.1 Determining the phase error
    2. 3.2 Converting to the time domain
    3. 3.3 Converting to modulator clock cycles
    4. 3.4 Converting to binary and writing to the PHASEn[9:0] bits
    5. 3.5 Phase calibration considerations
    6. 3.6 Summarizing the phase calibration process
    7. 3.7 Using the Phase Calibration Feature
      1. 3.7.1 Phase calibration considerations examples
  7. 4Synchronizing the ADS131M0x
    1. 4.1 The SYNC/RESET pin on the ADS131M0x
    2. 4.2 The importance of routing the clock signal
      1. 4.2.1 Single Clock Buffer
      2. 4.2.2 Multiple Clock Buffers
  8. 5Summary
  9. 6References

4.2.2 Multiple Clock Buffers

TI recommends using individual clock buffers for each ADC in systems with more than 4 channels. However, clock buffers introduce channel-to-channel clock skew that causes sampling skews between the ADCs. A high speed clock buffer such as LMK1C1104 has a well specified 50ps channel-to-channel output skew specification. General purpose logic buffers often have unspecified or excessively large output skew specifications of several nanoseconds. These general purpose logic buffers can often be used for low clock speeds but must be evaluated for the specific application requirements.