SDAA451 July   2026 ADS131M08

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2What is phase shift and phase error?
  6. 3How to calibrate out phase error with the ADS131M08
    1. 3.1 Determining the phase error
    2. 3.2 Converting to the time domain
    3. 3.3 Converting to modulator clock cycles
    4. 3.4 Converting to binary and writing to the PHASEn[9:0] bits
    5. 3.5 Phase calibration considerations
    6. 3.6 Summarizing the phase calibration process
    7. 3.7 Using the Phase Calibration Feature
      1. 3.7.1 Phase calibration considerations examples
  7. 4Synchronizing the ADS131M0x
    1. 4.1 The SYNC/RESET pin on the ADS131M0x
    2. 4.2 The importance of routing the clock signal
      1. 4.2.1 Single Clock Buffer
      2. 4.2.2 Multiple Clock Buffers
  8. 5Summary
  9. 6References

Using the Phase Calibration Feature

The following example compares an ADS131M08 channel with phase calibration enabled to one with no programmed phase calibration. Figure 3-1 shows a recreation of the DRDY signals of two ADS131M08 channels: ADS131M08(0) in red and ADS131M08(1) in black.

 DRDY signals for two channels with no phase calibration appliedFigure 3-1 DRDY signals for two channels with no phase calibration applied

This DRDY̅ timing difference is the digital equivalent of the waveforms shown in Figure 3-2, where the load phase angle,φ,and the phase error, φ, are both present.

 two measured signals with shift of φ +∆φFigure 3-2 two measured signals with shift of φ +φ.

The φ is the unwanted phase error that needs to be removed by applying a phase shift to the ADS131M08 channels.

Assume the 38tMOD (9.28µs) from Equation 13 has been converted to binary and programmed into the PHASE0[9:0] register of ADS131M08(0). Figure 3-3 shows the DRDY̅ signals with a positive phase shift of 9.28μs applied to ADS131M08(0).

 DRDY signals for two channels with 9.28µs phase shift applied to channel 0Figure 3-3 DRDY signals for two channels with 9.28µs phase shift applied to channel 0

With the phase error compensated, the resulting signals are corrected. Figure 3-4 shows the two measured signals after phase compensation is applied; the φ component is removed, leaving only the intended load phase angle φ.

 two measured signals with shift of φFigure 3-4 two measured signals with shift of φ